公开(公告)号：US09953934B2

公开(公告)日：2018-04-24

申请号：US14971744

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Siddarth Kumar ,  Sandeep B Sane ,  Shubhada H. Sahasrabudhe ,  Shalabh Tandon

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/16

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A warp controlled package includes a substrate that assumes a warped configuration according to the application of heat. At least one device is coupled along the substrate. A plurality of electrical contacts extend between at least the device and the substrate. One or more counter moment elements are coupled with the substrate. The one or more counter moment elements include a passive configuration and a counter moment configuration. In the counter moment configuration the one or more counter moment elements are configured to apply a counter moment to the substrate to counteract the warped configuration. In the passive configuration the one or more counter moment elements are configured to apply a neutral counter moment less than the counter moment of the counter moment configuration.

公开(公告)号：US09659908B1

公开(公告)日：2017-05-23

申请号：US14937022

申请日：2015-11-10

Applicant: Intel Corporation

Inventor： Shubhada H. Sahasrabudhe ,  Sandeep B Sane ,  Siddarth Kumar ,  Shalabh Tandon

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/1607 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81193 ,  H01L2224/81365 ,  H01L2224/81815 ,  H01L2224/81951 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815

Abstract: Discussed generally herein are methods and devices for more reliable Package on Package (PoP) Through Mold Interconnects (TMIs). A device can include a first die package including a first conductive pad on or at least partially in the first die package, a dielectric mold material on the first die package, the mold material including a hole therethrough at least partially exposing the pad, a second die package including a second conductive pad on or at least partially in the second die package the second die package on the mold material such that the second conductive pad faces the first conductive pad through the hole, and a shape memory structure in the hole and forming a portion of a solder column electrical connection between the first die package and the second die package.