公开(公告)号：US20230118079A1

公开(公告)日：2023-04-20

申请号：US17877540

申请日：2022-07-29

Applicant: ATI TECHNOLOGIES ULC

Inventor： Jun LEI ,  Syed Athar HUSSAIN ,  David I.J. GLEN ,  Rajeevan PANCHACHARAMOORTHY ,  Fatemeh AMIRNAVAEI ,  David GALIFFI ,  Arshad RAHMAN ,  Boris IVANOVIC

IPC: G09G5/12 ,  G06F3/14

Abstract: A display system modifies display cycles of one or more displays to perform a system operation while avoiding visual perturbations at the one or more displays. The display system modifies, synchronizes, or both, blanking periods of the one or more displays such that blanking periods equal or exceed a blackout duration and overlap for at least the blackout duration. Then the system performs the system operation during an overlapping portion of the one or more blanking periods, where the system operation reduces availability of display data at the one or more displays.

公开(公告)号：US20230110765A1

公开(公告)日：2023-04-13

申请号：US17889956

申请日：2022-08-17

Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC.

Inventor： Benjamin Koon Pan CHAN ,  William Lloyd Atkinson ,  Tung Chuen Kwong ,  Guhan Krishnan

IPC: G06F21/62 ,  G06V10/94

Abstract: A computer vision processor in an image cluster defines a fenced memory region (FMR) that controls access to image data stored in a first portion of a trusted memory region (TMR). The computer vision processor receives FMR requests from an application implemented in a processing cluster. The FMR requests are to access the image data in the first portion of the TMR. The computer vision processor selectively allows the requesting application to access the image data. In some cases, the computer vision processor acquires the image data and stores the image data in the first portion of the TMR, such as buffers in the TMR. A data fabric selectively permits the image processing application to access the data stored in the TMR based on whether the image cluster has opened or closed the FMR for the portion of the TMR.

公开(公告)号：US20230101770A1

公开(公告)日：2023-03-30

申请号：US17489286

申请日：2021-09-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： SUMING HU ,  FARSHAD GHAHGHAHI ,  ANDREW KWAN WAI LEUNG

IPC: H01L21/673 ,  H01L21/67 ,  H01L21/02

Abstract: A carrier boat for die package flux cleaning, including: a body having at least one pair of substantially parallel sides, the body comprising one or more die package receptacles each oriented at a non-parallel angle relative to the substantially parallel sides of the body such that, when a die package is seated in a die package receptacle of the one or more die package receptacles, a first pair of opposing sides of a die of the die package are substantially perpendicular to the substantially parallel sides,

公开(公告)号：US20230100409A1

公开(公告)日：2023-03-30

申请号：US17490964

申请日：2021-09-30

Applicant: ATI Technologies ULC

Inventor： Danial Yahyazadeh ,  Philippe Blanchard

IPC: G06F1/26 ,  G06F13/38 ,  G06F13/40 ,  G06T1/20 ,  H02M1/00

Abstract: A power supply circuit is provided for supplying power from multiple peripheral power supplies to a data processor. The power supply circuit includes a power bus, a plurality of load voltage converters each including an input coupled to the power bus and an output coupled to a respective one of multiple subsystems of the data processor, a plurality of input voltage converters each including an input for coupling to a respective one of multiple peripheral power supply voltages and an output coupled to the power bus, and a feedback control circuit having an input coupled to the power bus and a plurality of outputs coupled to respective ones of the input voltage converters for controlling a current draw of the respective input voltage converter.

公开(公告)号：US20230097620A1

公开(公告)日：2023-03-30

申请号：US18073719

申请日：2022-12-02

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Guennadi Riguer ,  Brian K. Bennett

IPC: G06T1/60 ,  G06F9/54 ,  G06F3/06 ,  G06F9/50 ,  G06F12/02 ,  G06T1/20 ,  G09G5/36

Abstract: Methods are provided for creating objects in a way that permits an API client to explicitly participate in memory management for an object created using the API. Methods for managing data object memory include requesting memory requirements for an object using an API and expressly allocating a memory location for the object based on the memory requirements. Methods are also provided for cloning objects such that a state of the object remains unchanged from the original object to the cloned object or can be explicitly specified.

公开(公告)号：US20230095785A1

公开(公告)日：2023-03-30

申请号：US17485736

申请日：2021-09-27

Applicant: ATI TECHNOLOGIES ULC

Inventor： VLADIMIR LACHINE

IPC: G06T5/00 ,  G06T7/90

Abstract: Chroma correction of inverse gamut mapping (IGM) for standard dynamic range (SDR) to high dynamic range (HDR) image conversion includes: converting R,G,B color components in the RGB color format of a pixel of an image to an intensity component (I) and chroma components (Ct and Cp) of an ICtCp color format, wherein the R,G,B color components represent red, green, and blue colors; applying an intensity transformation operation on the intensity component (I) of the pixel; executing a chroma correction operation on the transformed intensity component (I) and the chroma components (Ct and Cp) of the pixel; and converting the intensity component (I) and the chroma components (Ct and Cp) of the pixel back to the RGB color format.

公开(公告)号：US11604753B2

公开(公告)日：2023-03-14

申请号：US17121371

申请日：2020-12-14

Applicant: ATI TECHNOLOGIES ULC

Inventor： Serguei Sagalovitch ,  Ilya Panfilov

IPC: G06F13/40 ,  G06F13/20 ,  G06F12/02

Abstract: The present disclosure relates to techniques for facilitating communication and memory transfer between PCIe devices that permit access to an entire address space even though a limited address space is exposed and/or visible via the PCIe BAR registers. To this end, the present disclosure aims to permit memory transfer of large blocks of memory from one device to another including memory invisible to the system (i.e. not exposed via PCIe BAR registers). For example, in some embodiments, a data packet may be received at a port associated with a processor interconnect. The data packet includes a header which contains a first address associated with the port. In response to identifying the first address from the first data packet at the port, the data packet is decoded. During the decoding process, a second address is identified in a payload of the data packet. The second address corresponds to a first memory location, and data associated with the payload of the data packet is then stored to the first memory location.

公开(公告)号：US11604655B2

公开(公告)日：2023-03-14

申请号：US17095904

申请日：2020-11-12

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Wentao Xu ,  Randall Alexander Brown ,  Vaibhav Amarayya Hiremath ,  Shijie Che ,  Kamraan Nasim

IPC: G06F9/44 ,  G06F9/4401

Abstract: In a system with a master processor and slave processors, sync points are used in boot instructions. While executing the boot instructions, the slave processor determines whether the sync point is enabled. In response to determining the sync point is enabled, the slave processor pauses execution of the boot instructions, waits for commands from the master processor, receives commands from the master processor, executes the received commands until a release command is received, and then continues to execute boot instructions. In response to determining the sync point is not enabled, the slave processor continues to execute boot instructions.

公开(公告)号：US20230055695A1

公开(公告)日：2023-02-23

申请号：US18045128

申请日：2022-10-07

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anirudh R. Acharya ,  Michael J. Mantor ,  Rex Eldon McCrary ,  Anthony Asaro ,  Jeffrey Gongxian Cheng ,  Mark Fowler

IPC: G06F9/48 ,  G06F9/52 ,  G06F9/54 ,  G06F12/1009 ,  G06F12/14 ,  G06T1/20

Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.

公开(公告)号：US20230031099A1

公开(公告)日：2023-02-02

申请号：US17963729

申请日：2022-10-11

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： BRYAN BLACK ,  MICHAEL Z. SU ,  GAMAL REFAI-AHMED ,  JOE SIEGEL ,  SETH PREJEAN

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00

Abstract: A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.