公开(公告)号：US08822989B2

公开(公告)日：2014-09-02

申请号：US13613178

申请日：2012-09-13

Applicant: Shunpei Yamazaki ,  Atsuo Isobe ,  Toshinari Sasaki

Inventor： Shunpei Yamazaki ,  Atsuo Isobe ,  Toshinari Sasaki

IPC: H01L29/10 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/7869 ,  H01L27/12 ,  H01L27/1225 ,  H01L29/10 ,  H01L29/41733 ,  H01L29/41775

Abstract: Provided is a semiconductor device including a transistor with large on-state current even when it is miniaturized. The transistor includes a pair of first conductive films over an insulating surface; a semiconductor film over the pair of first conductive films; a pair of second conductive films, with one of the pair of second conductive films and the other of the pair of second conductive films being connected to one of the pair of first conductive films and the other of the pair of first conductive films, respectively; an insulating film over the semiconductor film; and a third conductive film provided in a position overlapping with the semiconductor film over the insulating film. Further, over the semiconductor film, the third conductive film is interposed between the pair of second conductive films and away from the pair of second conductive films.

Abstract translation: 提供了即使在小型化时也具有大导通状态的晶体管的半导体装置。 晶体管包括在绝缘表面上的一对第一导电膜; 在一对第一导电膜上的半导体膜; 一对第二导电膜，其中一对第二导电膜中的一个和一对第二导电膜中的另一个分别连接到一对第一导电膜中的一个和一对第一导电膜中的另一个; 半导体膜上的绝缘膜; 以及设置在与绝缘膜上的半导体膜重叠的位置的第三导电膜。 此外，在半导体膜之上，第三导电膜插入在一对第二导电膜之间并远离一对第二导电膜。

公开(公告)号：US08815657B2

公开(公告)日：2014-08-26

申请号：US12550540

申请日：2009-08-31

Applicant: Suguru Ozawa ,  Atsuo Isobe ,  Takashi Hamada ,  Junpei Momo ,  Hiroaki Honda ,  Takashi Shingu ,  Tetsuya Kakehata

Inventor： Suguru Ozawa ,  Atsuo Isobe ,  Takashi Hamada ,  Junpei Momo ,  Hiroaki Honda ,  Takashi Shingu ,  Tetsuya Kakehata

IPC: H01L21/00

CPC classification number: H01L21/76254

Abstract: After a single crystal semiconductor layer provided over a base substrate by attaching is irradiated with a laser beam, characteristics thereof are improved by first heat treatment, and after adding an impurity element imparting conductivity to the single crystal semiconductor layer, second heat treatment is performed at lower temperature than that of the first heat treatment.

Abstract translation: 在通过附着设置在基底基板上的单晶半导体层通过激光照射之后，通过第一热处理来提高其特性，并且在向单晶半导体层添加赋予导电性的杂质元素之后，进行第二热处理 比第一次热处理温度低。

公开(公告)号：US08809854B2

公开(公告)日：2014-08-19

申请号：US13446020

申请日：2012-04-13

Applicant: Atsuo Isobe ,  Toshinari Sasaki

Inventor： Atsuo Isobe ,  Toshinari Sasaki

IPC: H01L29/10

CPC classification number: H01L29/78696 ,  H01L21/02565 ,  H01L21/02592 ,  H01L21/02667 ,  H01L23/564 ,  H01L27/1052 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/24 ,  H01L29/4236 ,  H01L29/42384 ,  H01L29/51 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Stable electric characteristics and high reliability are provided to a miniaturized and integrated semiconductor device including an oxide semiconductor. In a transistor (a semiconductor device) including an oxide semiconductor film, the oxide semiconductor film is provided along a trench (groove) formed in an insulating layer. The trench includes a lower end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and the oxide semiconductor film is provided in contact with a bottom surface, the lower end corner portion, and an inner wall surface of the trench. The oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface at least over the lower end corner portion.

Abstract translation: 将稳定的电特性和高可靠性提供给包括氧化物半导体的小型化和集成的半导体器件。 在包括氧化物半导体膜的晶体管（半导体器件）中，氧化物半导体膜沿着形成在绝缘层中的沟槽（沟槽）设置。 沟槽包括具有曲率半径大于或等于20nm且小于或等于60nm的弯曲形状的下端拐角部分，并且氧化物半导体膜设置成与底表面接触，下端 拐角部分和沟槽的内壁表面。 氧化物半导体膜包括具有基本上垂直于至少在下端拐角部分的表面的c轴的晶体。

公开(公告)号：US08686315B2

公开(公告)日：2014-04-01

申请号：US11433670

申请日：2006-05-15

Applicant: Koichiro Tanaka ,  Hidekazu Miyairi ,  Aiko Shiga ,  Akihisa Shimomura ,  Atsuo Isobe

Inventor： Koichiro Tanaka ,  Hidekazu Miyairi ,  Aiko Shiga ,  Akihisa Shimomura ,  Atsuo Isobe

IPC: B23K26/073 ,  H01L21/268

CPC classification number: H01L21/02675 ,  B23K26/0604 ,  B23K26/0608 ,  B23K26/0732 ,  B23K26/0736 ,  B23K26/0738 ,  B23K26/352 ,  B23K2101/40 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/268 ,  H01L21/283 ,  H01L27/1285 ,  H01L27/1296 ,  H01L27/14625

Abstract: The present invention is characterized in that by laser beam being slantly incident to the convex lens, an aberration such as astigmatism or the like is occurred, and the shape of the laser beam is made linear on the irradiation surface or in its neighborhood. Since the present invention has a very simple configuration, the optical adjustment is easier, and the device becomes compact in size. Furthermore, since the beam is slantly incident with respect to the irradiated body, the return beam can be prevented.

Abstract translation: 本发明的特征在于，通过激光束倾斜地入射到凸透镜，发生像散等像，并且激光束的形状在照射表面或其附近被制成线性的。 由于本发明具有非常简单的结构，因此光学调节更容易，并且器件尺寸变得紧凑。 此外，由于光束相对于照射体倾斜入射，所以可以防止返回光束。

公开(公告)号：US08569753B2

公开(公告)日：2013-10-29

申请号：US13117588

申请日：2011-05-27

Applicant: Atsuo Isobe ,  Yoshinori Ieda ,  Keitaro Imai ,  Kiyoshi Kato ,  Yuto Yakubo ,  Yuki Hata

Inventor： Atsuo Isobe ,  Yoshinori Ieda ,  Keitaro Imai ,  Kiyoshi Kato ,  Yuto Yakubo ,  Yuki Hata

IPC: H01L21/02

CPC classification number: H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1225 ,  H01L28/60

Abstract: The semiconductor device is provided in which a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is arranged in matrix and a wiring (also referred to as a bit line) for connecting one of the memory cells and another one of the memory cells and a source or drain region in the first transistor are electrically connected through a conductive layer and a source or drain electrode in the second transistor provided therebetween. With this structure, the number of wirings can be reduced in comparison with a structure in which the source or drain electrode in the first transistor and the source or drain electrode in the second transistor are connected to different wirings. Thus, the integration degree of a semiconductor device can be increased.

Abstract translation: 提供了一种半导体器件，其中包括第一晶体管，第二晶体管和电容器的多个存储单元被布置成矩阵，并且布线（也称为位线）用于连接其中一个存储单元和另一个 第一晶体管中的一个存储单元和源极或漏极区域通过导电层和设置在其间的第二晶体管中的源极或漏极电连接。 利用这种结构，与第一晶体管中的源极或漏极以及第二晶体管中的源极或漏极连接到不同布线的结构相比，可以减少布线的数量。 因此，可以提高半导体器件的集成度。

公开(公告)号：US08450123B2

公开(公告)日：2013-05-28

申请号：US13213458

申请日：2011-08-19

Applicant: Yutaka Okazaki ,  Keitaro Imai ,  Atsuo Isobe ,  Shunpei Yamazaki

Inventor： Yutaka Okazaki ,  Keitaro Imai ,  Atsuo Isobe ,  Shunpei Yamazaki

IPC: H01L21/66

CPC classification number: G01N23/2258 ,  G01N2223/611

Abstract: Experience shows that, in a material containing oxygen as a main component, an excess or deficiency of trace amounts of oxygen with respect to a stoichiometric composition, or the like affects properties of the material. An oxygen diffusion evaluation method of an oxide film stacked body includes the steps of: measuring a quantitative value of one of oxygen isotopes of a substrate including a first oxide film and a second oxide film which has an existence proportion of an oxygen isotope different from an existence proportion of an oxygen isotope in the first oxide film in a depth direction, by secondary ion mass spectrometry; and evaluating the one of the oxygen isotopes diffused from the first oxide film to the second oxide film.

Abstract translation: 经验表明，在含氧作为主要成分的材料中，相对于化学计量组成等的痕量氧的过量或不足影响材料的性能。 氧化膜层叠体的氧扩散评价方法包括以下步骤：测量包含第一氧化物膜和第二氧化物膜的基板的氧同位素的定量值，所述氧化物存在比例与氧同位素 通过二次离子质谱法在深度方向上在第一氧化膜中的氧同位素的存在比例; 并评估从第一氧化物膜扩散到第二氧化物膜的氧同位素中的一种。

公开(公告)号：US20130075722A1

公开(公告)日：2013-03-28

申请号：US13613192

申请日：2012-09-13

Applicant: Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Yutaka OKAZAKI ,  Takehisa HATANO ,  Sachiaki TEZUKA ,  Suguru HONDO ,  Toshihiko SAITO

Inventor： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Yutaka OKAZAKI ,  Takehisa HATANO ,  Sachiaki TEZUKA ,  Suguru HONDO ,  Toshihiko SAITO

IPC: H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/42384 ,  H01L29/78618 ,  H01L29/7869

Abstract: A highly reliable structure for high-speed response and high-speed driving of a semiconductor device, in which on-state characteristics of a transistor are increased is provided. In the coplanar transistor, an oxide semiconductor layer, a source and drain electrode layers including a stack of a first conductive layer and a second conductive layer, a gate insulating layer, and a gate electrode layer are sequentially stacked in this order. The gate electrode layer is overlapped with the first conductive layer with the gate insulating layer provided therebetween, and is not overlapped with the second conductive layer with the gate insulating layer provided therebetween.

Abstract translation: 提供了一种用于高速响应和高速驱动半导体器件的高度可靠的结构，其中晶体管的导通状态特性增加。 在共面晶体管中，依次层叠氧化物半导体层，包括第一导电层和第二导电层的堆叠的源极和漏极电极层，栅极绝缘层和栅极电极层。 栅极电极层与第一导电层重叠，栅极绝缘层设置在它们之间，并且与其间设置有栅极绝缘层的第二导电层不重叠。

公开(公告)号：US20120267709A1

公开(公告)日：2012-10-25

申请号：US13446026

申请日：2012-04-13

Applicant: Atsuo ISOBE ,  Toshinari SASAKI

Inventor： Atsuo ISOBE ,  Toshinari SASAKI

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/78603 ,  H01L29/4236 ,  H01L29/42384 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a highly reliable semiconductor device. To provide a semiconductor device which prevents a defect and achieves miniaturization. An oxide semiconductor layer in which the thickness of a region serving as a source region or a drain region is larger than the thickness of a region serving as a channel formation region is formed in contact with an insulating layer including a trench. In a transistor including the oxide semiconductor layer, variation in threshold voltage, degradation of electric characteristics, and shift to normally on can be suppressed and source resistance or drain resistance can be reduced, so that the transistor can have high reliability.

Abstract translation: 提供高度可靠的半导体器件。 提供一种防止缺陷并实现小型化的半导体器件。 形成与包括沟槽的绝缘层接触的用作源区或漏区的区域的厚度大于用作沟道形成区的区的厚度的氧化物半导体层。 在包括氧化物半导体层的晶体管中，可以抑制阈值电压的变化，电特性的劣化和正常的导通，可以降低源电阻或漏极电阻，从而晶体管可以具有高的可靠性。

公开(公告)号：US08253140B2

公开(公告)日：2012-08-28

申请号：US13012448

申请日：2011-01-24

Applicant: Hiroshi Shibata ,  Atsuo Isobe

Inventor： Hiroshi Shibata ,  Atsuo Isobe

IPC: H01L29/04 ,  H01L27/01

CPC classification number: H01L27/1255 ,  G02F1/133345 ,  G02F1/13454 ,  G02F1/136209 ,  G02F1/136213 ,  G02F1/136227 ,  G02F1/136277 ,  G02F1/136286 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/3244 ,  H01L27/3248 ,  H01L27/3262 ,  H01L27/3265 ,  H01L27/3276 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/78633

Abstract: To provide a liquid crystal display device having high quality display by obtaining a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the load. A scanning line is formed on a different layer from a gate electrode and the capacitor wiring is arranged so as to be parallel with a signal line. Each pixel is connected to the individually independent capacitor wiring via a dielectric. Therefore, variations in the electric potential of the capacitor wiring caused by a writing-in electric current of a neighboring pixel can be avoided, whereby obtaining satisfactory display images.

Abstract translation: 为了提供一种通过在确保足够的存储电容器（Cs）的同时获得高开口率而具有高质量显示的液晶显示装置，并且同时通过分散电容器布线的负载（像素写入电流） 及时有效减轻负荷。 扫描线形成在与栅电极不同的层上，电容布线与信号线平行。 每个像素通过电介质连接到单独独立的电容器布线。 因此，可以避免由相邻像素的写入电流引起的电容器布线的电位变化，从而获得令人满意的显示图像。

公开(公告)号：US20110297928A1

公开(公告)日：2011-12-08

申请号：US13117588

申请日：2011-05-27

Applicant: Atsuo ISOBE ,  Yoshinori IEDA ,  Keitaro IMAI ,  Kiyoshi KATO ,  Yuto YAKUBO ,  Yuki HATA

Inventor： Atsuo ISOBE ,  Yoshinori IEDA ,  Keitaro IMAI ,  Kiyoshi KATO ,  Yuto YAKUBO ,  Yuki HATA

IPC: H01L27/105

CPC classification number: H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1225 ,  H01L28/60

Abstract: The semiconductor device is provided in which a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is arranged in matrix and a wiring (also referred to as a bit line) for connecting one of the memory cells and another one of the memory cells and a source or drain region in the first transistor are electrically connected through a conductive layer and a source or drain electrode in the second transistor provided therebetween. With this structure, the number of wirings can be reduced in comparison with a structure in which the source or drain electrode in the first transistor and the source or drain electrode in the second transistor are connected to different wirings. Thus, the integration degree of a semiconductor device can be increased.

Abstract translation: 提供了一种半导体器件，其中包括第一晶体管，第二晶体管和电容器的多个存储单元被布置成矩阵，并且布线（也称为位线）用于连接其中一个存储单元和另一个 第一晶体管中的一个存储单元和源极或漏极区域通过导电层和设置在其间的第二晶体管中的源极或漏极电连接。 利用这种结构，与第一晶体管中的源极或漏极以及第二晶体管中的源极或漏极连接到不同布线的结构相比，可以减少布线的数量。 因此，可以提高半导体器件的集成度。