公开(公告)号：US5923664A

公开(公告)日：1999-07-13

申请号：US824941

申请日：1997-03-27

Applicant: Jean-Paul Aldebert ,  Jean Calvignac ,  Daniel Orsatti ,  Fabrice Verplanken ,  Jean-Claude Zunino

Inventor： Jean-Paul Aldebert ,  Jean Calvignac ,  Daniel Orsatti ,  Fabrice Verplanken ,  Jean-Claude Zunino

IPC: H04L12/70 ,  H04Q11/04 ,  H04J3/16 ,  H04J3/22 ,  H04J3/24

CPC classification number: H04Q11/0478 ,  H04L2012/5615

Abstract: The invention discloses a method and an apparatus for implementing the physical interface in a network element connected to a packet network such as Asynchronous Transfer Mode (ATM) network. With the solution of the invention, the physical interface functions can be integrated on one chip for more than one network port. The physical interface is provided between port bit streams at media speed and word data flow transferred onto/from a bus which is under the control of the network equipment. The solution of the invention includes grouping logics and storage elements by islands of more than one port. Furthermore, the logics and storage elements for statistical counting operations can be grouped for a processing generalized to all ports. Finally, the solution of the present invention takes into account two characteristics of the physical interface which are the different rates between network link media speed and bus access rate and the technology of the high density static imbedded RAMs used for hardware integration. The Flip/Flop pointer RAMs of Flip/Flop data RAMs are duplicated and some interface RAMs are created to transfer control data between the islands and the generalized processing logical blocks.

Abstract translation: 本发明公开了一种在连接到诸如异步传输模式（ATM）网络的分组网络的网络元件中实现物理接口的方法和装置。 通过本发明的解决方案，物理接口功能可以集成在多个网络端口的一个芯片上。 在媒体速度的端口比特流之间提供物理接口，并且传输到/经由网络设备控制的总线上的字数据流。 本发明的解决方案包括通过多于一个端口的岛分组逻辑和存储元件。 此外，用于统计计数​​操作的逻辑和存储元件可以被分组用于对所有端口进行泛化。 最后，本发明的解决方案考虑了物理接口的两个特征，它们是网络链路媒体速度和总线访问速率之间的不同速率以及用于硬件集成的高密度静态嵌入RAM的技术。 翻转/翻转数据RAM的翻转/翻转指针RAM被复制，并且创建一些接口RAM以在岛和广义处理逻辑块之间传送控制数据。

公开(公告)号：US5561807A

公开(公告)日：1996-10-01

申请号：US234193

申请日：1994-04-28

Applicant: Fabrice Verplanken ,  Claude Basso ,  Didier Giroir ,  Jean Calvignac ,  Claude Galand

Inventor： Fabrice Verplanken ,  Claude Basso ,  Didier Giroir ,  Jean Calvignac ,  Claude Galand

IPC: G06F13/00 ,  G06F15/16 ,  G06F15/177 ,  H04L12/18

CPC classification number: H04L12/18

Abstract: An apparatus and method for multicasting messages stored in data buffers of a data storage. Each message is composed of data stored in a plurality of the data buffers. Each data buffer is controlled and mapped to a unique direct control block (DCB) which stores information characterizing the data buffer. By chaining the DCBs variable length, messages can be generated. Indirect control blocks (ICB) stores information characterizing the data or messages duplicated and points to a DCB. A field in the DCB carries a count representing the number of times the message is to be duplicated.

公开(公告)号：US5325404A

公开(公告)日：1994-06-28

申请号：US836492

申请日：1992-02-18

Applicant: Jean-Claude Bigey ,  Jean Calvignac ,  Jean-Christophe Debos ,  Rene Gallezot ,  Eric Saint-Georges

Inventor： Jean-Claude Bigey ,  Jean Calvignac ,  Jean-Christophe Debos ,  Rene Gallezot ,  Eric Saint-Georges

IPC: H04J3/06 ,  H04L7/00 ,  H04Q11/04

CPC classification number: H04J3/062 ,  H04Q11/04

Abstract: In a communication node (10) which comprises switching device (24) operating under control of a clock signal of period T for exchanging information slots carried in external frames of period T' comprising n slots, with each slot comprising a x-bit data byte, between external Time Division Multiplex TDM links (12,14) attached to the communication node, a synchronization device prevents the slippage phenomena due to the asynchronies between T and T' from causing a loss of data slots by generating at the input of the switching means internal frames from the received external frames. These internal frames are synchronous with the clock signal of period T and have a format which allows the slippage to be compensated.

Abstract translation: 在包括在周期T的时钟信号的控制下操作的交换设备（24）的通信节点（10）中，用于交换在包括n个时隙的周期T'的外部帧中携带的信息时隙，每个时隙包括x位数据字节 ，在连接到通信节点的外部时分复用TDM链路（12,14）之间，同步设备防止由于T和T'之间的异步而导致的数据时隙的丢失导致在切换的输入处产生的滑动现象 指从接收的外部帧的内部帧。 这些内部帧与周期T的时钟信号同步，并具有允许补偿滑动的格式。

公开(公告)号：US5251206A

公开(公告)日：1993-10-05

申请号：US684111

申请日：1991-04-12

Applicant: Jean Calvignac ,  Eric Saint Georges ,  Daniel Orsatti ,  Gilles Toubol ,  Fabrice Verplanken ,  Francois Nicolas

Inventor： Jean Calvignac ,  Eric Saint Georges ,  Daniel Orsatti ,  Gilles Toubol ,  Fabrice Verplanken ,  Francois Nicolas

IPC: H04Q3/52 ,  H04L12/64 ,  H04L12/56 ,  H04L12/50

CPC classification number: H04L12/64

Abstract: The hybrid packet and circuit switching system allows merging of packet and circuit traffic from user interface modules on a TDM bus and transfer of packet information from one module to another module or the exchange circuit information between modules. Circuit exchanges or packet transfers are performed synchronously on the TDM busses in bursts of period T, with each burst comprising a fixed number of bytes. The bursts are switched by switch 1. A routing indication common to the packet and circuit bursts is used for controlling the switching of the bursts by the switch 1. The indication is performed by piggy backing the target module address for the circuit bursts, as well as for the packet burst, with the data bursts. Marking tables needed for the circuit burst allocation are located in the user interface modules.

公开(公告)号：US5119478A

公开(公告)日：1992-06-02

申请号：US357225

申请日：1989-05-26

Applicant: Jean Calvignac ,  Jacques Feraud ,  Bernard Naudin ,  Claude Pin ,  Eric Saint-Georges

Inventor： Jean Calvignac ,  Jacques Feraud ,  Bernard Naudin ,  Claude Pin ,  Eric Saint-Georges

IPC: H04L29/02 ,  H04L29/06 ,  H04L29/08

CPC classification number: H04L29/06 ,  H04L69/12 ,  H04L69/324

Abstract: The bit streams, transporting the frames, received from lines (6) are placed in register 12 in such a way that n bits are processed in parallel during a time interval T. Parallel processor 10 counts the consecutive logical "1" bits beginning at the low order (left most) bit of the n bits received in interval T and from the bits received in the previous interval T-1, to determine when this number is found equal to 5 which bits have to be deleted, and when this number is found equal to 6 whether a flag is received. As a result, it reassembles N-bit characters, with N

公开(公告)号：US5119376A

公开(公告)日：1992-06-02

申请号：US506035

申请日：1990-04-06

Applicant: Mohamed Badaoui ,  Jean Calvignac ,  Guy Carle ,  Christian Garcia ,  Pierre Vachee

Inventor： Mohamed Badaoui ,  Jean Calvignac ,  Guy Carle ,  Christian Garcia ,  Pierre Vachee

IPC: H04L29/10 ,  G06F13/38

CPC classification number: G06F13/385

Abstract: Interconnection system for attaching a maximum number n of equipment users EU (DCE or DTE) to the line adapter (2) of a communication processing unit. The user data and control bits are carried on transmit and receive serial link 4 and 6 in data and control slot entities arranged in frame of period T, comprising one entity per user. These entities are allocated to the user equipments through multiplexing/demultiplexing circuit (10), link adapters (12-1) to (12-8) and connecting boxes (30-1) to (30-8). The user equipments are connected through active remote modules which are specific to the standardized interfaces of the user equipments. Link adapters (12-1) to (12-8) add to the data and control slot entities an outband slot which is used for exchanging control information, such as the active remote module address and type which are stored in memory (42), to be transmitted to the line adapter (2). The advantage of the interconnection system is that the attachment of the user equipments is simplified.

Abstract translation: 用于将最多数量的设备用户EU（DCE或DTE）附加到通信处理单元的线路适配器（2）的互连系统。 用户数据和控制位在周期T的帧中布置的数据和控制时隙实体中的发送和接收串行链路4和6上承载，每个用户包括一个实体。 这些实体通过复用/解复用电路（10），链路适配器（12-1）至（12-8）和连接盒（30-1）至（30-8）分配给用户设备。 用户设备通过用户设备标准接口专用的主动远程模块连接。 链路适配器（12-1）至（12-8）向数据和控制时隙实体添加用于交换诸如存储在存储器（42）中的主动远程模块地址和类型的控制信息的外带时隙， 被传送到线路适配器（2）。 互连系统的优点是简化了用户设备的连接。

公开(公告)号：US4799219A

公开(公告)日：1989-01-17

申请号：US77484

申请日：1987-07-24

Applicant: Jean Calvignac ,  Pierre Secondo

Inventor： Jean Calvignac ,  Pierre Secondo

IPC: H04L12/64 ,  H04J3/26

CPC classification number: H04L12/64

Abstract: A pseudo synchronous mechanism is used in the nodes of a communication network for exchanging non-character coded information (NCI) and potentially character coded information on inter node links. Communication is performed in frames comprising circuit slots devoted to the transportation of character coded information. The circuit slots are assigned to circuit users on a per-call basis under control of node management apparatus. The slots are qualified by at least one qualification bit (Caq) which indicates, when set to a first value (0) that the users are momentarily active and when set to a second value (1) that the users are momentarily inactive. The node mechanism includes a store in which queues of storing positions are assigned to the circuit users attached to the node. The circuit user information to be sent on the network internode links or received from the internode links is stored in the store. The node mechanism further includes an internode adapter which controls the generation and reception of the frames to and from each internode link. The adapter operates under control of a node manager which assigns on a per-call basis, a set of at least one slot in the frames transported on the network link to each of a plurality of circuit users. The node also includes transmit and receive controls which cause the queues assigned to the plurality of local users to be sequentially scanned and read from or written to according to whether the qualification bits are set to a first value.

公开(公告)号：US4491913A

公开(公告)日：1985-01-01

申请号：US433744

申请日：1982-10-12

Applicant: Jean Calvignac ,  Yves Granger ,  Andre Masclet

Inventor： Jean Calvignac ,  Yves Granger ,  Andre Masclet

IPC: H04L29/04 ,  G06F13/00 ,  G06F13/22 ,  G06F13/38 ,  G06F1/00

CPC classification number: G06F13/385 ,  G06F13/22

Abstract: The address generating device is provided for a communication line scanning device. The lines are connected to the scanning device through n line interface circuits, n varying in accordance with the network configuration. Each interface circuit can be connected to a various number of lines, for instance one line or k lines in a preferred embodiment, and comprises means for providing to the address generating device, a presence indicating signal indicating that it is plugged and a signal indicating the number of the lines connected thereto. A first logic circuit receives the presence indicating signals as inputs and generates on its outputs the address bits of the last present interface circuit to be scanned. A first counter able to count in binary mode up to n-1 is incremented by an increment pulse provided by a clock on each period assigned to the scanning of a line. This counter outputs the address bits of the successive interface circuits. A comparator compares the address bits so generated and the address bits of the last present interface circuit to be scanned and outputs a reset signal when these bits are equal.

Abstract translation: 为通信线扫描装置提供地址产生装置。 线路通过n线接口电路连接到扫描设备，n根据网络配置而变化。 每个接口电路可以连接到各种数量的线路，例如在优选实施例中的一条线路或k条线路，并且包括用于向地址生成设备提供指示其被插入的存在指示信号的装置和指示其的信号 与其连接的线数。 第一逻辑电路接收存在指示信号作为输入，并在其输出上产生要扫描的最后一个当前接口电路的地址位。 能够以二进制模式计数直到n-1的第一个计数器由分配给扫描行的每个周期上的时钟提供的增量脉冲递增。 该计数器输出连续接口电路的地址位。 一个比较器比较这样产生的地址位和最后一个当前接口电路的地址位，并在这些位相等时输出一个复位信号。