-
公开(公告)号：US20200044606A1
公开(公告)日：2020-02-06
申请号：US16527799
申请日：2019-07-31
Applicant: Stichting IMEC Nederland
Inventor： Paul Mateman , Cui Zhou
IPC: H03B5/12
Abstract: A differential Colpitts oscillator circuit is described which has center-tapped inductors which are cross-coupled with gates of second transistors of first and second transistor pairs which can reduce the minimum power supply voltage and the bias voltage for the circuit. In addition, a capacitive ladder can be implemented which also has the potential benefit of increased tuning range.
-
公开(公告)号：US20190190465A1
公开(公告)日：2019-06-20
申请号：US16222340
申请日：2018-12-17
Applicant: Stichting IMEC Nederland
Inventor： Elbert Bechthum , Ao Ba
CPC classification number: H03F3/005 , H03F1/0211 , H03F3/193 , H03F3/2171 , H03F3/2178 , H03F3/3028 , H03F3/3064 , H03F3/72 , H03F2200/09 , H03F2200/312 , H03F2200/417 , H03F2200/421 , H03F2200/451 , H03F2200/48
Abstract: A switched-capacitor power amplifier comprising a plurality of cells and methods for its operation are described. Switched signal lines switch supply to respective capacitors. Switches connect respective signal lines to a first supply and switches connect respective signal lines to a second supply. Pairs of switches on each signal line are switched so that one is switched off whilst the other is switched on. In a “full amplitude” mode, operation of the switches provides an output having a peak determined by the first supply. A switch signal line is provided between nodes in respective signal lines, a switch being provided in the switch signal line. In a “half amplitude” mode, switch is switched at the radio frequency in the other direction to that of switches connecting the signal lines to respective ones of the first and second supplies with the other switches being kept open.
-
公开(公告)号：US20190187263A1
公开(公告)日：2019-06-20
申请号：US16224124
申请日：2018-12-18
Applicant: Stichting IMEC Nederland
Inventor： Jac Romme
Abstract: A method for determining a distance between a first radio signal transceiver and a second radio signal transceiver using narrowband ranging comprises calculating a preliminary estimate of a value proportional to a one-way frequency domain channel response, based on measurements of signal phase and signal strength; calculating, for pairs of adjacent frequencies, an estimate of a value proportional to a time synchronization offset between a clock used by the first radio signal transceiver and a clock used by the second radio signal transceiver, and determining a final estimate of a value proportional to the one-way frequency domain channel response based on the preliminary estimate and adjacent estimates for the value proportional to the time synchronization offset, where the final estimate is used for the final distance determination.
-
公开(公告)号：US20180337683A1
公开(公告)日：2018-11-22
申请号：US15985563
申请日：2018-05-21
Applicant: Stichting IMEC Nederland
Inventor： Paul Mateman
CPC classification number: H03L7/0992 , H03L7/081 , H03L7/091 , H03L7/18 , H04L1/205 , H04L7/0331
Abstract: Systems and methods for providing improved linearity and reduced noise in a digital phase-locked loop in which a differential time-to-digital converter is implemented. Digital-to-time converters are used for adjusting a reference clock signal based on a fractional change signal and for adjusting a feedback signal based on another fractional change signal. Each fractional change signal is centered about a midpoint, M, and offset from the midpoint by a fraction, x, such that the fractional change signals can be described as (M+x) and (M−x), respectively. By implementing a differential time-to-digital converter, the sum of delays in each input path is kept constant so that integral non-linearity is improved. Supply sensitivity is also reduced, as the same supply is applied to both differential input paths. Since the differential delay can be both positive and negative, the delay range of a differential digital-to-time converter is half that of a single input digital-to-time converter.
-
公开(公告)号：US20180231997A1
公开(公告)日：2018-08-16
申请号：US15890336
申请日：2018-02-06
Applicant: Stichting IMEC Nederland
Inventor： Stefano STANZIONE
Abstract: According to an aspect of the present inventive concept there is provided voltage reference generator comprising: a voltage reference, a variable gain amplifier connected to an output terminal of the voltage reference, a sampling capacitor connected to an output terminal of the voltage reference generator and further connected to an output terminal of the variable gain amplifier via a sampling switch, said switch being adapted to close during a first portion of a switching period of said switch and said switch being adapted to open during a second portion of the switching period, a ripple monitor adapted to estimate a magnitude of variation of an output voltage of the voltage reference generator resulting from charging and discharging of the sampling capacitor, and to, based on the estimate, perform one of: control of the sampling switch to reduce a switching frequency of the sampling switch to increase a magnitude of the variation of the output voltage, and control of the sampling switch to increase the switching frequency, to decrease a magnitude of the variation of the output voltage. There is also provided a method.
-
Patent Agency Ranking
公开(公告)号：US10027339B2
公开(公告)日：2018-07-17
申请号：US15833796
申请日：2017-12-06
Applicant: Stichting IMEC Nederland
Inventor： Ming Ding , Pieter Harpe , Hanyue Li
CPC classification number: H03M1/1023 , H03M1/0675 , H03M1/1033 , H03M1/1047 , H03M1/108 , H03M1/44 , H03M1/46 , H03M1/462 , H03M1/468
Abstract: A method of DAC mismatch calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (VIN), detecting if a binary code determined from the analog input signal (VIN) matches at least one trigger code, using at least one setting code to determine a calibration residue signal (V*RES) and a calibration bit (B*LSB), analyzing a least significant bit of the digital signal (COUT) and the calibration bit (B*LSB), determining an indication of a presence of DAC mismatch, and calibrating the DAC mismatch. As the determination of the calibration bit (B*LSB) requires only one additional comparison, when compared to the normal operation, the normal operation does not need to be interrupted. Therefore, the calibration can be done in the background and, as such, can be performed frequently thereby taking into account time-varying changes due to environmental effects.
-
公开(公告)号：US20180167078A1
公开(公告)日：2018-06-14
申请号：US15833796
申请日：2017-12-06
Applicant: Stichting IMEC Nederland
Inventor： Ming Ding , Pieter Harpe , Hanyue Li
CPC classification number: H03M1/1023 , H03M1/0675 , H03M1/1033 , H03M1/1047 , H03M1/108 , H03M1/44 , H03M1/46 , H03M1/462 , H03M1/468
Abstract: A method of DAC mismatch calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (VIN), detecting if a binary code determined from the analog input signal (VIN) matches at least one trigger code, using at least one setting code to determine a calibration residue signal (V*RES) and a calibration bit (B*LSB), analyzing a least significant bit of the digital signal (COUT) and the calibration bit (B*LSB), determining an indication of a presence of DAC mismatch, and calibrating the DAC mismatch. As the determination of the calibration bit (B*LSB) requires only one additional comparison, when compared to the normal operation, the normal operation does not need to be interrupted. Therefore, the calibration can be done in the background and, as such, can be performed frequently thereby taking into account time-varying changes due to environmental effects.
-
公开(公告)号：US20180055409A1
公开(公告)日：2018-03-01
申请号：US15689930
申请日：2017-08-29
Applicant: Stichting IMEC Nederland
Inventor： Jiawei XU
Abstract: According to an aspect of the present inventive concept there is provided a reconfigurable sensor circuit comprising: an input stage including a first input terminal and a second input terminal, and an amplification stage including: a first amplifier having a non-inverting input, an inverting input and an output connected to the inverting input of the first amplifier via a first resistor, a second amplifier having a non-inverting input, an inverting input and an output connected to the inverting input of the second amplifier via a second resistor, and first switching circuitry adapted to be arranged in a first state, wherein the amplification stage is in a differential amplifier configuration, and in a second state, wherein the amplification stage is in a transimpedance amplifier configuration, wherein, in the differential amplifier configuration, the first amplifier and the second amplifier are together configured as a differential amplifier connected to the first and the second input terminals, and wherein, in the transimpedance amplifier configuration, at least the first amplifier is configured as a transimpedance amplifier connected to the first input terminal.
-
公开(公告)号：US20170346493A1
公开(公告)日：2017-11-30
申请号：US15605261
申请日：2017-05-25
Applicant: IMEC VZW , Stichting IMEC Nederland , Vrije Universiteit Brussel
Inventor： Nereo Markulic , Yao-Hong Liu , Jan Craninckx
CPC classification number: H03L7/085 , H03K5/159 , H03K2005/00013 , H03L7/081 , H03L7/0991 , H03L7/197 , H03L7/1976 , H03L2207/50
Abstract: The disclosure provides a phase locked loop, PLL, for phase locking an output signal to a reference signal. The PLL comprises a reference path providing the reference signal to a first input of a phase detector, a feedback loop providing the output signal of the PLL as a feedback signal to a second input of the phase detector, a controllable oscillator generating the output signal based on at least a phase difference between reference and feedback signal, a digital-to-time converter, DTC, delaying a signal that is provided at one of the first and second input, a delay calculation path for calculating a DTC delay value. The PLL further comprises a randomization unit for generating and adding a random offset, i.e. a pseudo-random integer, to the delay value. The offset is such that a target output of the phase detector remains substantially unchanged.
-
100.发明授权公开(公告)号：US09759558B2
公开(公告)日：2017-09-12
申请号：US14471158
申请日：2014-08-28
Applicant: Stichting IMEC Nederland
Inventor： Marco Altini
IPC: G01N33/48 , G01N33/50 , G01B21/00 , A61B5/0205 , A61B5/11 , A61B5/16 , A61B5/00 , G06F17/10 , G06F19/12 , G01C22/00 , A61B5/024 , A61B5/08 , A61B5/053
CPC classification number: G01B21/00 , A61B5/0002 , A61B5/0205 , A61B5/02055 , A61B5/02438 , A61B5/0533 , A61B5/0816 , A61B5/1112 , A61B5/1118 , A61B5/1123 , A61B5/165 , A61B5/4866 , A61B5/6802 , A61B2560/0223 , G01C22/00 , G01C22/006 , G06F17/10 , G06F19/12
Abstract: An example device includes: a data input module configured to receive information about a living being's physiological signals, coordinates, and motion intensity; an activity recognition module configured to calculate, from information received about the living being's motion intensity, a living being's activity; a location recognition module, configured to calculate, from information received about the living being's coordinates, a living being's location; a memory storage configured to store information about the living being's physiological signals and activity in association with the location; a normalization parameters estimator module configured to use a mathematical model to calculate a plurality of normalization parameters for a plurality of detected activities and locations; and a model selector module configured to determine, based on the plurality of normalization parameters and the living being's location, a set of location-specific normalization parameters used to further calculate normalized physiological signals for the living being.
-
-
-
-
-
-
-
-
-
Search Results
329
records
(took 0.021 seconds)
