公开(公告)号：US10235290B2

公开(公告)日：2019-03-19

申请号：US14752408

申请日：2015-06-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Gabriel H. Loh ,  Mitesh R. Meswani

IPC: G06F12/02 ,  G06F12/0811 ,  G06F12/0897 ,  G06F12/1027

Abstract: Systems, apparatuses, and methods for sorting memory pages in a multi-level heterogeneous memory architecture. The system may classify pages into a first “hot” category or a second “cold” category. The system may attempt to place the “hot” pages into the memory level(s) closest to the systems' processor cores. The system may track parameters associated with each page, with the parameters including number of accesses, types of accesses, power consumed per access, temperature, wearability, and/or other parameters. Based on these parameters, the system may generate a score for each page. Then, the system may compare the score of each page to a threshold. If the score of a given page is greater than the threshold, the given page may be designated as “hot”. If the score of the given page is less than the threshold, the given page may be designated as “cold”.

公开(公告)号：US10073746B2

公开(公告)日：2018-09-11

申请号：US15207943

申请日：2016-07-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Taniya Siddiqua ,  Vilas Sridharan

IPC: G06F11/00 ,  G06F11/14 ,  G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0631 ,  G06F3/067 ,  G06F11/2058 ,  G06F11/2069 ,  G06F2201/84

Abstract: Methods and apparatus presented herein provide distributed checkpointing in a multi-node system, such as a network of servers in a data center. When checkpointing of application state data is needed in a node, the methods and apparatus determine whether checkpoint memory space is available in the node for checkpointing the application state data. If not enough checkpoint memory space is available in the node, the methods and apparatus request and find additional checkpoint memory space from other nodes in the system. In this manner, the methods and apparatus can checkpoint the application state data into available checkpoint memory spaces distributed among a plurality of nodes. This allows for high bandwidth and low latency checkpointing operations in the multi-node system.

公开(公告)号：US10019283B2

公开(公告)日：2018-07-10

申请号：US14746601

申请日：2015-06-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Dmitri Yudanov ,  Sergey Blagodurov ,  Arkaprava Basu ,  Sooraj Puthoor ,  Joseph L. Greathouse

IPC: G06F9/46 ,  G06F9/30

CPC classification number: G06F9/461 ,  G06F9/3013 ,  G06F9/3851

Abstract: A processing device includes a first memory that includes a context buffer. The processing device also includes a processor core to execute threads based on context information stored in registers of the processor core and a memory controller to selectively move a subset of the context information between the context buffer and the registers based on one or more latencies of the threads.

公开(公告)号：US20160378668A1

公开(公告)日：2016-12-29

申请号：US14747967

申请日：2015-06-23

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Sergey Blagodurov

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F2212/6024

Abstract: A memory module stores memory access metadata reflecting information about memory accesses to the memory module. The memory access metadata can indicate the number of times a particular unit of data (e.g., a row of data, a unit of data corresponding to a cache line, and the like) has been read, written, had one or more of its bits flipped, and the like. Modifications to the embedded access metadata can be made by a control module at the memory module itself, thereby reducing overhead at a processor core. In addition, the control module can be configured to record different access metadata for different memory locations of the memory module.

Abstract translation: 存储器模块存储反映关于存储器模块的存储器访问的信息的存储器访问元数据。 存储器访问元数据可以指示已读取，写入的特定数据单元（例如，一行数据，对应于高速缓存行等的数据单元等）的次数具有其位中的一个或多个 翻转等。 嵌入式访问元数据的修改可以由存储器模块本身的控制模块进行，从而减少处理器核心的开销。 此外，控制模块可以被配置为记录存储器模块的不同存储器位置的不同访问元数据。

公开(公告)号：US20160246540A1

公开(公告)日：2016-08-25

申请号：US14629014

申请日：2015-02-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Andrew G. Kegel

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0647 ,  G06F3/0607 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/067 ,  G06F12/0215 ,  G06F2212/654

Abstract: In one form, scheduling data migration comprises determining whether the data is likely to be used by an input/output (I/O) device, the data being at a location remote to the I/O device; and scheduling the data for migration from the remote location to a location local to the I/O device in response to determining that the data is likely to be used by the I/O device.

Abstract translation: 在一种形式中，调度数据迁移包括确定数据是否可能被输入/输出（I / O）设备使用，该数据位于远离I / O设备的位置; 并且响应于确定数据可能被I / O设备使用而调度用于从远程位置迁移到I / O设备本地的位置的数据。

公开(公告)号：US20160179382A1

公开(公告)日：2016-06-23

申请号：US14576912

申请日：2014-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Mitesh Ramesh Meswani ,  Gabriel H. Loh ,  Mauricio Breternitz, JR. ,  Mark Richard Nutter ,  John Robert Slice ,  David Andrew Roberts ,  Michael Ignatowski ,  Mark Henry Oskin

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/061 ,  G06F3/0634 ,  G06F3/0673 ,  G06F3/0685

Abstract: A processor modifies memory management mode for a range of memory locations of a multilevel memory hierarchy based on changes in an application phase of an application executing at a processor. The processor monitors the application phase (e.g.,. computation-bound phase, input/output phase, or memory access phase) of the executing application and in response to a change in phase consults a management policy to identify a memory management mode. The processor automatically reconfigures a memory controller and other modules so that a range of memory locations of the multilevel memory hierarchy are managed according to the identified memory management mode. By changing the memory management mode for the range of memory locations according to the application phase, the processor improves processing efficiency and flexibility.

Abstract translation: 处理器基于在处理器上执行的应用的应用阶段的变化来修改多层存储器层级的一系列存储器位置的存储器管理模式。 处理器监视执行应用程序的应用阶段（例如，计算限制阶段，输入/输出阶段或存储器访问阶段）并且响应于阶段的改变来咨询管理策略以识别存储器管理模式。 处理器自动重新配置存储器控制器和其他模块，使得根据所识别的存储器管理模式来管理多级存储器层级的一系列存储器位置。 通过根据应用阶段改变存储器位置范围的存储器管理模式，处理器提高了处理效率和灵活性。