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    Sensor-type package and fabrication method thereof
    92.
    发明申请
    Sensor-type package and fabrication method thereof 审中-公开
    传感器型封装及其制造方法

    公开(公告)号：US20080079105A1

    公开(公告)日：2008-04-03

    申请号：US11904648

    申请日：2007-09-27

    Applicant: Tse-Wen Chang ,  Chang-Yueh Chan ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

    Inventor： Tse-Wen Chang ,  Chang-Yueh Chan ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

    IPC: H01L31/0203 ,  H01L21/02

    CPC classification number: H01L27/14618 ,  H01L24/97 ,  H01L27/14683 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2224/85 ,  H01L2924/00014

    Abstract: A sensor-type package and a fabrication method thereof are provided. A sensor-type chip is mounted on a substrate and is electrically connected to the substrate via bonding wires. A light-pervious body is attached to the sensor-type chip, and has one surface covered with a covering layer and another surface formed with an adhesive layer. An encapsulant encapsulates the light-pervious body. As an adhesive force between the covering layer and the encapsulant is greater than that between the covering layer and the light-pervious body, the covering layer and a portion of the encapsulant located on the covering layer can be concurrently removed, such that the light-pervious body is exposed and light can pass through the light-pervious body to be captured by the sensor-type chip. The above arrangement eliminates the need of using a dam structure as in the prior art and provides a compact sensor-type package with improved fabrication reliability.

    Abstract translation: 提供了传感器型封装及其制造方法。 传感器型芯片安装在基板上，并通过接合线与基板电连接。 透光体附着在传感器型芯片上，其一个表面被覆盖层和形成有粘合剂层的另一表面覆盖。 密封剂封装透光体。 由于覆盖层和密封剂之间的粘合力大于覆盖层和透光体之间的粘合力，所以可以同时去除位于覆盖层上的覆盖层和密封剂的一部分， 透光体被曝光，光可以通过透光体，由传感器型芯片捕获。 上述布置消除了如现有技术中使用坝结构的需要，并且提供了具有改进的制造可靠性的紧凑型传感器型封装。

    Method for fabricating semiconductor packages
    93.
    发明授权
    Method for fabricating semiconductor packages 有权
    半导体封装的制造方法

    公开(公告)号：US07348211B2

    公开(公告)日：2008-03-25

    申请号：US11117158

    申请日：2005-04-27

    Applicant: Ying-Ren Lin ,  Ho-Yi Tsai ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

    Inventor： Ying-Ren Lin ,  Ho-Yi Tsai ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

    IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44

    CPC classification number: H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A method for fabricating semiconductor packages is proposed. A plurality of substrates each having a chip thereon are prepared. Each substrate has similar length and width to the predetermined length and width of the semiconductor package. A carrier having a plurality of openings is prepared. Each opening is larger in length and width than the substrate. The substrates are positioned in the corresponding openings, and gaps between the substrates and the carrier are sealed. A molding process is performed to form an encapsulant over each opening to encapsulate the chip. An area on the carrier covered by the encapsulant is larger in length and width than the opening. After performing a mold-releasing process, a plurality of the semiconductor packages are formed by a singulation process to cut along substantially edges of each substrate according to the predetermined size of the semiconductor package. A waste of substrate material is avoided.

    Abstract translation: 提出了制造半导体封装的方法。 制备各自具有芯片的多个基板。 每个衬底具有与半导体封装的预定长度和宽度相似的长度和宽度。 制备具有多个开口的载体。 每个开口的长度和宽度大于衬底。 基板定位在相应的开口中，基板和载体之间的间隙被密封。 执行成型工艺以在每个开口上形成密封剂以封装芯片。 由密封剂覆盖的载体上的区域的长度和宽度大于开口的宽度。 在执行脱模工艺之后，通过单片化工艺形成多个半导体封装，以根据半导体封装的预定尺寸沿着每个衬底的大致边缘切割。 避免了衬底材料的浪费。

    Semiconductor package, array arranged substrate structure for the semiconductor package and fabrication method of the semiconductor package
    95.
    发明申请
    Semiconductor package, array arranged substrate structure for the semiconductor package and fabrication method of the semiconductor package 审中-公开
    半导体封装，半导体封装的阵列排列衬底结构和半导体封装的制造方法

    公开(公告)号：US20070243666A1

    公开(公告)日：2007-10-18

    申请号：US11725512

    申请日：2007-03-19

    Applicant: Chien-Ping Huang ,  Chien-Chih Chen ,  Yu-Chieh Tsai

    Inventor： Chien-Ping Huang ,  Chien-Chih Chen ,  Yu-Chieh Tsai

    IPC: H01L21/00

    CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0256 ,  H05K1/0259 ,  H05K3/0052 ,  H05K3/242 ,  H05K3/284 ,  H05K2201/09063 ,  H05K2201/0909 ,  H01L2224/85 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

    Abstract: A semiconductor package, an array arranged substrate structure for the semiconductor package, and fabrication method of the semiconductor package are disclosed. First, a substrate having a plurality of array arranged substrate units is provided, and electroplating buses are formed between the substrate units. Each substrate unit has a plurality of electrically connecting pads and a plurality of conductive traces for connecting the electrically connecting pads to the electroplating buses such that an electroplating metallic layer can be formed on the electrically connecting pads via the electroplating buses and the conductive traces. Then, slots are further formed between the substrate units for disconnecting connections between the conductive traces and the electroplating buses, thus, enable each of the substrate units to become electrically independent from each other for a pre-proceeding electrical O/S test. Moreover, the slots are filled with a filling material such as an insulating gel or an encapsulant during a Molding process. Further, a cutting process is performed between the substrate units through the filling material or encapsulant filling the slots upon completion of encapsulation. Thus, the cutting surface can be kept smooth and exposure of conductive traces from the cutting surface is avoided, thereby preventing static electricity and humidity from adversely affecting the product quality.

    Abstract translation: 公开了半导体封装，用于半导体封装的阵列布置衬底结构以及半导体封装的制造方法。 首先，提供具有多个阵列排列的基板单元的基板，并且在基板单元之间形成电镀总线。 每个基板单元具有多个电连接焊盘和用于将电连接焊盘连接到电镀总线的多个导电迹线，使得可以经由电镀母线和导电迹线在电连接焊盘上形成电镀金属层。 然后，在衬底单元之间进一步形成槽，用于断开导电迹线和电镀母线之间的连接，从而使每个衬底单元彼此电独立以进行预处理电气O / S测试。 此外，在成型过程中，槽中填充诸如绝缘凝胶或密封剂的填充材料。 此外，在完成封装之后，通过填充材料或填充槽的密封剂在衬底单元之间进行切割处理。 因此，切割面可以保持平滑，并且避免了来自切割表面的导电迹线的暴露，从而防止静电和湿气对产品质量产生不利影响。

    Flip-chip semiconductor package with lead frame as chip carrier and fabrication method thereof
    96.
    发明授权
    Flip-chip semiconductor package with lead frame as chip carrier and fabrication method thereof 有权
    具有引线框架作为芯片载体的倒装芯片半导体封装及其制造方法

    公开(公告)号：US07274088B2

    公开(公告)日：2007-09-25

    申请号：US10196305

    申请日：2002-07-16

    Applicant: Chi-Chuan Wu ,  Chien-Ping Huang ,  Han-Ping Pu

    Inventor： Chi-Chuan Wu ,  Chien-Ping Huang ,  Han-Ping Pu

    IPC: H01L23/495 ,  H01L29/40

    CPC classification number: H01L24/16 ,  H01L23/4951 ,  H01L23/49558 ,  H01L23/49575 ,  H01L2224/13099 ,  H01L2224/16245 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00

    Abstract: A flip-ship semiconductor package with a lead frame as a chip carrier is provided, wherein a plurality of leads of the lead frame are each formed with at least a dam member thereon. When a chip is mounted on the lead frame by means of solder bumps, each of the solder bumps is attached to the corresponding one of the leads at a position between the dam member and an inner end of the lead. During a reflow-soldering process for wetting the solder bumps to the leads, the dam members would help control collapse height of the solder bumps, so as to enhance resistance of the solder bumps to thermal stress generated by CTE (coefficient of thermal expansion) mismatch between the chip and the leads, thereby preventing incomplete electrical connection between the chip and the leads.

    Abstract translation: 提供一种具有引线框架作为芯片载体的翻转半导体封装，其中引线框架的多个引线至少形成有至少一个阻挡构件。 当通过焊料凸块将芯片安装在引线框架上时，每个焊料凸块在引线的阻挡件和引线的内端之间的位置附接到相应的一个引线。 在用于将焊料凸点润湿到引线的回流焊接过程中，阻挡构件将有助于控制焊料凸块的塌陷高度，从而增强焊料凸块对CTE产生的热应力的阻力（热膨胀系数）不匹配 在芯片和引线之间，从而防止芯片和引线之间的不完全的电连接。

    Method for fabricating sensor semiconductor device
    97.
    发明授权
    Method for fabricating sensor semiconductor device 有权
    制造传感器半导体器件的方法

    公开(公告)号：US07271024B2

    公开(公告)日：2007-09-18

    申请号：US11163310

    申请日：2005-10-13

    Applicant: Chien-Ping Huang ,  Chih-Ming Huang ,  Cheng-Yi Chang

    Inventor： Chien-Ping Huang ,  Chih-Ming Huang ,  Cheng-Yi Chang

    IPC: H01L21/00 ,  H01L31/113

    CPC classification number: H01L27/14683 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14634 ,  H01L2224/81801 ,  H01L2224/82 ,  H01L2224/85 ,  H01L2224/86 ,  H01L2924/14 ,  H01L2924/00

    Abstract: A sensor semiconductor device and a method for fabricating the same are proposed. A plurality of metal bumps and a sensor chip are mounted on a substrate. A dielectric layer and a circuit layer are formed on the substrate, wherein the circuit layer is electrically connected to the metal bumps and the sensor chip. Thus, the sensor chip is electrically connected to the substrate via the circuit layer and the metal bumps. The dielectric layer is formed with an opening for exposing a sensor region of the sensor chip. A light-penetrable lid covers the opening of the dielectric layer, such that light is able to penetrate the light-penetrable lid to reach the sensor region and activate the sensor chip. A plurality of solder balls are mounted on a surface of the substrate free of mounting the sensor chip, for electrically connecting the sensor chip to an external device.

    Abstract translation: 提出了一种传感器半导体器件及其制造方法。 多个金属凸块和传感器芯片安装在基板上。 在基板上形成电介质层和电路层，其中电路层电连接到金属凸块和传感器芯片。 因此，传感器芯片经由电路层和金属凸块电连接到基板。 电介质层形成有用于暴露传感器芯片的传感器区域的开口。 透光盖子覆盖电介质层的开口，使得光线能够穿透透光盖子到达传感器区域并激活传感器芯片。 多个焊球安装在基板的表面上，无需安装传感器芯片，用于将传感器芯片电连接到外部设备。

    Photosensitive semiconductor package, method for fabricating the same, and lead frame thereof
    99.
    发明授权
    Photosensitive semiconductor package, method for fabricating the same, and lead frame thereof 有权
    感光半导体封装，其制造方法及其引线框架

    公开(公告)号：US07242068B2

    公开(公告)日：2007-07-10

    申请号：US10953915

    申请日：2004-09-28

    Applicant: Chien-Ping Huang

    Inventor： Chien-Ping Huang

    IPC: H01L31/0203 ,  H01L23/495

    CPC classification number: H01L31/0203 ,  H01L23/49861 ,  H01L27/14618 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

    Abstract: A photosensitive semiconductor package, a method for fabricating the same, and a lead frame thereof are proposed. The lead frame has a die pad and a plurality of leads, wherein at least one recessed portion is formed at an end of each lead close to the die pad, and at least one recessed region is formed on the die pad. An encapsulant fills the recessed portions, the recessed region, and between the leads and the die pad, and is formed on the lead frame to define a chip receiving cavity. A photosensitive chip is mounted in the chip receiving cavity, wherein at least partially a non-active surface of the chip is attached to the encapsulant filling the recessed region and is not in contact with the recessed region. A light-penetrable unit is attached to the encapsulant formed on the lead frame to seal the chip receiving cavity.

    Abstract translation: 提出了一种光敏半导体封装及其制造方法及其引线框架。 引线框架具有管芯焊盘和多个引线，其中至少一个凹部形成在靠近管芯焊盘的每个引线的端部处，并且至少一个凹陷区域形成在管芯焊盘上。 密封剂填充凹陷部分，凹陷区域以及引线和芯片焊盘之间，并且形成在引线框架上以限定芯片接收腔。 感光芯片安装在芯片接收腔中，其中至少部分地将芯片的非活性表面附着到填充凹陷区域并且不与凹陷区域接触的密封剂。 可透光单元连接到形成在引线框架上的密封剂以密封芯片接收腔。

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