公开(公告)号：US10785295B2

公开(公告)日：2020-09-22

申请号：US15199572

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Daniel Rivas Barragan ,  Kshitij A. Doshi ,  Mark A. Schmisseur ,  Steen Larsen

IPC: H04L29/08 ,  G06F3/06 ,  H04L12/931

Abstract: Fabric encapsulated resilient storage is hardware-assisted resilient storage in which the reliability capabilities of a storage server are abstracted and managed transparently by a host fabric interface (HFI) to a switch. The switch abstracts the reliability capabilities of a storage server into a level of resilience in a hierarchy of levels of resilience. The resilience levels are accessible by clients as a quantifiable characteristic of the storage server. The resilience levels are used by the switch fabric to filter which storage servers store objects responsive to client requests to store objects at a specified level of resilience.

公开(公告)号：US10771554B2

公开(公告)日：2020-09-08

申请号：US15721867

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Vadim Sukhomlinov ,  Kshitij A. Doshi ,  Edwin Verplanke

IPC: G06F13/00 ,  H04L29/08 ,  G06F9/46 ,  G06F9/455

Abstract: Disclosed embodiments relate to cloud scaling with non-blocking, non-spinning cross-domain event synchronization and data communication. In an example, a processor includes a memory to store multiple virtual hardware thread (VHTR) descriptors, each including an architectural state, a monitored address range, a priority, and an execution state, fetch circuitry to fetch instructions associated with a plurality of the multiple VNFs, decode circuitry to decode the fetched instructions, scheduling circuitry to allocate and pin a VHTR to each of the plurality of VNFs, schedule execution of a VHTR on each of a plurality of cores, set the execution state of the scheduled VHTR; and in response to a monitor instruction received from a given VHTR, pause the given VHTR and switch in another VHTR to use the core previously used by the given VHTR, and, upon detecting a store to the monitored address range, trigger execution of the given VHTR.

公开(公告)号：US10680976B2

公开(公告)日：2020-06-09

申请号：US15260638

申请日：2016-09-09

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Daniel Rivas Barragan ,  Alejandro Duran Gonzalez

IPC: H04L12/933 ,  H04L29/10

Abstract: Technologies for performing switch-based collective operations in a fabric architecture include a network switch communicatively coupled to a plurality of computing nodes. The network switch is configured to identify sub-operations of a collective operation of a collective operation request received from one of the computing nodes and identify a plurality of operands for each of the sub-operations. The network switch is additionally configured to request a value for each of the operands from a corresponding target computing node at which the respective value is stored, determine a result of the collective operation as a function of the requested operand values, and transmit the result to the requesting computing node. Other embodiments are described herein.

公开(公告)号：US20190353502A1

公开(公告)日：2019-11-21

申请号：US16466770

申请日：2017-01-03

Applicant: INTEL CORPORATION

Inventor： Kshitij A. Doshi ,  Tao Zhong ,  Gang Deng ,  Zhongyan Lu

IPC: G01D3/08 ,  G01D3/10 ,  H04L29/08

Abstract: A system and method for managing sensors including determining health operation states of the sensors correlative with sensor accuracy, classifying the sensors by their respective health operation state, and teaming two sensors each having a health operation state that is intermediate to give a team having a health operation state that is healthy. The sampling frequency of the sensors to determine sensor accuracy may be dynamic.

公开(公告)号：US20190140838A1

公开(公告)日：2019-05-09

申请号：US16234724

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Johan Van De Groenendaal ,  Kshitij A. Doshi ,  Susanne M. Balle ,  Suraj Prabhakaran

IPC: H04L9/32 ,  H04L9/08

Abstract: Technologies for providing certified telemetry data indicative of resource utilizations include a device with circuitry configured to obtain telemetry data indicative of a utilization of one or more device resources over a time period. The circuitry is additionally configured to sign the obtained telemetry data with a private key associated with the present device. Further, the circuitry is configured to send the signed telemetry data to a telemetry service for analysis

公开(公告)号：US20190102357A1

公开(公告)日：2019-04-04

申请号：US15721529

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Dmitry Y. Babokin ,  Kshitij A. Doshi ,  Vadim Sukhomlinov

IPC: G06F17/16 ,  G06F9/30

Abstract: Detailed are embodiments related to bit matrix multiplication in a processor. For example, in some embodiments a processor comprising: decode circuitry to decode an instruction have fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and an immediate; and execution circuitry to execute the decoded instruction to perform a multiplication of a matrix of S-bit elements of the identified first source bit matrix with S-bit elements of the identified second source bit matrix, wherein the multiplication and accumulation operations are selected by the operation selector and store a result of the matrix multiplication into the identified destination bit matrix, wherein S indicates a plural bit size is described.

公开(公告)号：US10248488B2

公开(公告)日：2019-04-02

申请号：US14983026

申请日：2015-12-29

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Suleyman Sair ,  Kshitij A. Doshi ,  Charles R. Yount

IPC: G06F11/16 ,  G06F11/07 ,  G06F9/30 ,  G06F9/38 ,  G06F9/455 ,  G06F15/80

Abstract: Systems, methods, and apparatuses for fault tolerance and detection are described. For example, an apparatus including circuitry to replicate input sources of an instruction; arithmetic logic unit (ALU) circuitry to execute the instruction with replicated input sources using single instruction, multiple data (SIMD) hardware to produce a packed data result; and comparison circuitry coupled to the ALU circuitry to evaluate the packed data result and output a singular data result into a destination of the instruction is described.

公开(公告)号：US20190007334A1

公开(公告)日：2019-01-03

申请号：US15639641

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Mark A. Schmisseur ,  Narayan Ranganathan ,  John Chun Kwok Leung

IPC: H04L12/911 ,  G06F13/40 ,  G06F9/455 ,  H04L12/40

Abstract: A host fabric interface (HFI) apparatus, including: an HFI to communicatively couple to a fabric; and a remote hardware acceleration (RHA) engine to: query an orchestrator via the fabric to identify a remote resource having an accelerator; and send a remote accelerator request to the remote resource via the fabric.

公开(公告)号：US10120814B2

公开(公告)日：2018-11-06

申请号：US15089211

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Kshitij A. Doshi ,  Christopher J. Hughes

IPC: G06F12/00 ,  G06F12/1045 ,  G06F12/1009 ,  G06F13/00 ,  G06F13/28

Abstract: An apparatus and method are described for managing TLB coherence. For example, one embodiment of a processor comprises: one or more cores to execute instructions and process data; one or more translation lookaside buffers (TLBs) each comprising a plurality of entries to cache virtual-to-physical address translations usable by the set of one or more cores when executing the instructions; one or more epoch counters each programmed with a specified epoch value; and TLB validation logic to validate a specified set of TLB entries at intervals specified by the epoch value.

公开(公告)号：US10095629B2

公开(公告)日：2018-10-09

申请号：US15279319

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Francesc Cesc Guim Bernat ,  Kshitij A. Doshi ,  Steen Larsen ,  Mark A Schmisseur ,  Raj K. Ramanujan

IPC: G06F13/00 ,  G06F12/10

Abstract: Generally discussed herein are systems, devices, and methods for local and remote dual address decoding. According to an example a node can include one or more processors to generate a first memory request, the first memory request including a first address and a node identification, a caching agent coupled to the one or more processors, the caching agent to determine that the first address is homed to a remote node remote to the local node, a network interface controller (NIC) coupled to the caching agent, the NIC to produce a second memory request based on the first memory request, and the one or more processors further to receive a response to the second memory request, the response generated by a switch coupled to the NIC, the switch includes a remote system address decoder to determine a node identification to which the second memory request is homed.