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    Leading change anticipator logic
    91.
    发明授权
    Leading change anticipator logic 有权
    领先的变化预测逻辑

    公开(公告)号：US09274752B2

    公开(公告)日：2016-03-01

    申请号：US13729421

    申请日：2012-12-28

    Applicant: Intel Corporation

    Inventor： Simon Rubanovich ,  Thierry Pons ,  Amit Gradstein ,  Zeev Sperber

    IPC: G06F7/74 ,  G06F5/01 ,  G06F7/485

    CPC classification number: G06F7/74 ,  G06F5/012 ,  G06F7/485

    Abstract: In one embodiment, a processor includes at least one floating point unit. The at least one floating point unit may include an adder, leading change anticipator (LCA) logic, and a shifter. The adder may be to add a first operand X and a second operand Y to obtain an output operand having a bit length n. The LCA logic may be to: for each bit position i from n−1 to 1, obtain a set of propagation values and a set of bit values based on the first operand X and the second operand Y; and generate a LCA mask based on the set of propagation values and the set of bit values. The shifter may be to normalize the output operand based on the LCA mask. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括至少一个浮点单元。 所述至少一个浮点单元可以包括加法器，引导改变预测器（LCA）逻辑和移位器。 加法器可以添加第一操作数X和第二操作数Y以获得具有位长度n的输出操作数。 LCA逻辑可以是：对于从n-1到1的每个比特位置i，基于第一操作数X和第二操作数Y获得一组传播值和一组比特值; 并且基于传播值集合和位值集合来生成LCA掩码。 移位器可以是基于LCA掩码来规范化输出操作数。 描述和要求保护其他实施例。

    Apparatus and method for conjugate transpose and multiply
    93.
    发明授权
    Apparatus and method for conjugate transpose and multiply 有权

    公开(公告)号：US12216734B2

    公开(公告)日：2025-02-04

    申请号：US17133456

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Menachem Adelman ,  Robert Valentine ,  Daniel Towner ,  Amit Gradstein ,  Mark Jay Charney

    IPC: G06F17/16 ,  G06F7/523 ,  G06F7/78 ,  G06F9/30

    Abstract: An apparatus and method for complex matrix conjugation and multiplication. For example, one embodiment of a processor comprises: a decoder to decode a complex matrix conjugation and multiplication instruction including a first source operand to identify a first complex source matrix comprising a first plurality of complex values, a second source operand to identify a second complex source matrix comprising a second plurality of complex values, and a first destination operand to identify a result matrix; execution circuitry to execute the complex matrix conjugation and multiplication instruction, the execution circuitry comprising: matrix conjugation hardware logic to determine a plurality of complex conjugate values corresponding to the first plurality of complex values; transpose hardware logic to transpose the plurality of complex conjugate values to generate a conjugate transpose matrix comprising the complex conjugate values; parallel multiplication circuitry to: multiply real values from the plurality of complex conjugate values of the conjugate transpose matrix with corresponding imaginary values from the second plurality of complex values to generate a first plurality of imaginary products, and multiply imaginary values from the plurality of complex conjugate values of the conjugate transpose matrix with corresponding real values from the second plurality of complex values to generate a second plurality of imaginary products; and addition/subtraction circuitry to add each imaginary product in the first plurality of imaginary products to a corresponding imaginary product in the second plurality of imaginary products to produce a corresponding imaginary component in the result matrix.

    SYSTEMS, APPARATUSES, AND METHODS FOR ADDITION OF PARTIAL PRODUCTS
    94.
    发明申请
    SYSTEMS, APPARATUSES, AND METHODS FOR ADDITION OF PARTIAL PRODUCTS 有权

    公开(公告)号：US20250004763A1

    公开(公告)日：2025-01-02

    申请号：US18886639

    申请日：2024-09-16

    Applicant: INTEL CORPORATION

    Inventor： Robert Valentine ,  Galina Ryvchin ,  Piotr Majcher ,  Mark J. Charney ,  Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal ,  Milind B. Girkar ,  Zeev Sperber ,  Simon Rubanovich ,  Amit Gradstein

    IPC: G06F9/30 ,  G06F7/544 ,  G06F9/38

    Abstract: Embodiments of systems, apparatuses, and methods for fused multiple add. In some embodiments, a decoder decodes a single instruction having an opcode, a destination field representing a destination operand, and fields for a first, second, and third packed data source operand, wherein packed data elements of the first and second packed data source operand are of a first, different size than a second size of packed data elements of the third packed data operand. Execution circuitry then executes the decoded single instruction to perform, for each packed data element position of the destination operand, a multiplication of a M N-sized packed data elements from the first and second packed data sources that correspond to a packed data element position of the third packed data source, add of results from these multiplications to a full-sized packed data element of a packed data element position of the third packed data source, and storage of the addition result in a packed data element position destination corresponding to the packed data element position of the third packed data source, wherein M is equal to the full-sized packed data element divided by N.

    Instructions to convert from FP16 to BF8
    95.
    发明授权
    Instructions to convert from FP16 to BF8 有权

    公开(公告)号：US12135968B2

    公开(公告)日：2024-11-05

    申请号：US17134358

    申请日：2020-12-26

    Applicant: Intel Corporation

    Inventor： Alexander Heinecke ,  Naveen Mellempudi ,  Robert Valentine ,  Mark Charney ,  Christopher Hughes ,  Evangelos Georganas ,  Zeev Sperber ,  Amit Gradstein ,  Simon Rubanovich

    IPC: G06F9/30 ,  G06F5/01

    Abstract: Techniques for converting FP16 to BF8 using bias are described. An exemplary embodiment utilizes decoder circuitry to decode a single instruction, the single instruction to include one or more fields to identify a first source operand, one or more fields to identify a second source operand, one or more fields to identify a source/destination operand, and one or more fields for an opcode, wherein the opcode is to indicate that execution circuitry is to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source/destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source/destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source/destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source/destination operand.

    Apparatuses, methods, and systems for instructions of a matrix operations accelerator
    96.
    发明授权
    Apparatuses, methods, and systems for instructions of a matrix operations accelerator 有权

    公开(公告)号：US11714875B2

    公开(公告)日：2023-08-01

    申请号：US16729361

    申请日：2019-12-28

    Applicant: Intel Corporation

    Inventor： Amit Gradstein ,  Simon Rubanovich ,  Sagi Meller ,  Saeed Kharouf ,  Gavri Berger ,  Zeev Sperber ,  Jose Yallouz ,  Ron Schneider

    IPC: G06F17/16 ,  G06F9/30 ,  G06F9/38 ,  G06F9/34

    CPC classification number: G06F17/16 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3851 ,  G06F9/34

    Abstract: Systems, methods, and apparatuses relating to a matrix operations accelerator are described. In one embodiment, a processor includes a matrix operations accelerator circuit that includes a two-dimensional grid of fused multiply accumulate circuits that is switchable to a scheduling mode for execution of a decoded single instruction where the matrix operations accelerator circuit loads a first buffer of the two-dimensional grid of fused multiply accumulate circuits from a first plurality of registers that represents a first input two-dimensional matrix, checks if a second buffer of the two-dimensional grid of fused multiply accumulate circuits stores an immediately prior input two-dimension matrix that is the same as a second input two-dimensional matrix from a second plurality of registers that represents the first input two-dimensional matrix, and when the second buffer of the two-dimensional grid of fused multiply accumulate circuits stores the immediately prior input two-dimension matrix, from execution of a previous instruction, that is the same as the second input two-dimensional matrix: prevents reclamation of the second buffer between execution of the previous instruction and the decoded single instruction, performs an operation on the first input two-dimensional matrix from the first buffer and the immediately prior input two-dimension matrix from the second buffer to produce a resultant, and stores the resultant in resultant storage, and when the second buffer of the two-dimensional grid of fused multiply accumulate circuits does not store the immediately prior input two-dimension matrix, from execution of the previous instruction, that is the same as the second input two-dimensional matrix: loads the second input two-dimensional matrix into the second buffer of the two-dimensional grid of fused multiply accumulate circuits, performs the operation on the first input two-dimensional matrix from the first buffer and the second input two-dimension matrix from the second buffer to produce a resultant, and stores the resultant in the resultant storage.

    Apparatuses, methods, and systems for hashing instructions
    99.
    发明授权
    Apparatuses, methods, and systems for hashing instructions 有权

    公开(公告)号：US11681530B2

    公开(公告)日：2023-06-20

    申请号：US17688728

    申请日：2022-03-07

    Applicant: Intel Corporation

    Inventor： Regev Shemy ,  Zeev Sperber ,  Wajdi Feghali ,  Vinodh Gopal ,  Amit Gradstein ,  Simon Rubanovich ,  Sean Gulley ,  Ilya Albrekht ,  Jacob Doweck ,  Jose Yallouz ,  Ittai Anati

    IPC: G06F9/30 ,  G06F9/38 ,  H04L9/06

    CPC classification number: G06F9/30145 ,  G06F9/30043 ,  G06F9/30196 ,  G06F9/3887 ,  H04L9/0643

    Abstract: Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described. In one embodiment, a processor includes a decode circuit to decode a single instruction into a decoded single instruction, the single instruction including at least one first field that identifies eight 32-bit state elements A, B, C, D, E, F, G, and H for a round according to a SM3 hashing standard and at least one second field that identifies an input message; and an execution circuit to execute the decoded single instruction to: rotate state element C left by 9 bits to form a rotated state element C, rotate state element D left by 9 bits to form a rotated state element D, rotate state element G left by 19 bits to form a rotated state element G, rotate state element H left by 19 bits to form a rotated state element H, perform two rounds according to the SM3 hashing standard on the input message and state element A, state element B, rotated state element C, rotated state element D, state element E, state element F, rotated state element G, and rotated state element H to generate an updated state element A, an updated state element B, an updated state element E, and an updated state element F, and store the updated state element A, the updated state element B, the updated state element E, and the updated state element F into a location specified by the single instruction.

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