公开(公告)号：US20190288176A1

公开(公告)日：2019-09-19

申请号：US16302049

申请日：2016-06-13

Applicant: Intel Corporation

Inventor： Zachary R. Yoscovits ,  David J. Michalak ,  Jeanette M. Roberts ,  Ravi Pillarisetty ,  James S. Clarke

IPC: H01L39/22 ,  H01L39/24 ,  G06N10/00

Abstract: Described herein are structures that include Josephson Junctions to be used in superconducting qubits of quantum circuits disposed on a substrate. In one aspect of the present disclosure, at least a part of a Josephson Junction of a superconducting qubit is suspended over a substrate, forming a gap between at least the portion of the Josephson Junction and the substrate. Moving at least a portion of the Josephson Junction further away from the substrate by suspending at least a part of the Junction over the substrate allows reducing spurious two-level systems present in the vicinity of the Junction, which, in turn, improves on the qubit decoherence problem. Methods for fabricating such structures are disclosed as well.

公开(公告)号：US20190259850A1

公开(公告)日：2019-08-22

申请号：US16307853

申请日：2016-06-09

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Van H. Le ,  Jeanette M. Roberts ,  David J. Michalak ,  James S. Clarke ,  Zachary R. Yoscovits

IPC: H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

Abstract: Disclosed herein are quantum dot devices with trenched substrates, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate having a trench disposed therein, wherein a bottom of the trench is provided by a first material, and a quantum well stack at least partially disposed in the trench. A material of the quantum well stack may be in contact with the bottom of the trench, and the material of the quantum well stack may be different from the first material.

公开(公告)号：US10388848B2

公开(公告)日：2019-08-20

申请号：US15924410

申请日：2018-03-19

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  James S. Clarke ,  Jessica M. Torres ,  Lester Lampert ,  Ravi Pillarisetty ,  Hubert C. George ,  Kanwaljit Singh ,  Jeanette M. Roberts ,  Roman Caudillo ,  Zachary R. Yoscovits ,  David J. Michalak

IPC: H01L39/02 ,  H01L39/04 ,  H01L39/22 ,  H01L39/24 ,  H03K17/92 ,  G06N10/00

Abstract: Embodiments of the present disclosure describe use of isotopically purified materials in donor- or acceptor-based spin qubit devices and assemblies. An exemplary spin qubit device assembly may include a semiconductor host layer that includes an isotopically purified material, a dopant atom in the semiconductor host layer, and a gate proximate to the dopant atom. An isotopically purified material may include a lower atomic-percent of isotopes with nonzero nuclear spin than the natural abundance of those isotopies in the non-isotopically purified material. Reducing the presence of isotopes with nonzero nuclear spin in a semiconductor host layer may improve qubit coherence and thus performance of spin qubit devices and assemblies.

公开(公告)号：US20190252377A1

公开(公告)日：2019-08-15

申请号：US16340512

申请日：2016-12-24

Applicant: Intel Corporation

Inventor： James S. Clarke ,  Nicole K. Thomas ,  Zachary R. Yoscovits ,  Hubert C. George ,  Jeanette M. Roberts ,  Ravi Pillarisetty

IPC: H01L27/088 ,  G06N10/00 ,  H01L29/778 ,  H01L29/66 ,  H01L27/18 ,  H01L21/8234

CPC classification number: H01L27/088 ,  B82Y10/00 ,  G06N10/00 ,  H01L21/823456 ,  H01L27/18 ,  H01L29/66977 ,  H01L29/778

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous rows extending in a first direction, and the plurality of second gates are arranged in electrically continuous rows extending in a second direction perpendicular to the first direction.

公开(公告)号：US10347834B2

公开(公告)日：2019-07-09

申请号：US15928220

申请日：2018-03-22

Applicant: INTEL CORPORATION

Inventor： Nicole K. Thomas ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Hubert C. George ,  Jeanette M. Roberts ,  David J. Michalak ,  Roman Caudillo ,  Zachary R. Yoscovits ,  Lester Lampert ,  James S. Clarke

IPC: H01L49/00 ,  G02B6/12 ,  G06N10/00 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y20/00

Abstract: Embodiments of the present disclosure propose two methods for integrating vacancy centers (VCs) on semiconductor substrates for forming VC-based spin qubit devices. The first method is based on using a self-assembly process for integrating VC islands on a semiconductor substrate. The second method is based on using a buffer layer of a III-N semiconductor material over a semiconductor substrate, and then integrating VC islands in an insulating carbon-based material such as diamond that is either grown as a layer on the III-N buffer layer or grown in the openings formed in the III-N buffer layer. Integration of VC islands on semiconductor substrates typically used in semiconductor manufacturing according to any of these methods may provide a substantial improvement with respect to conventional approaches to building VC-based spin qubit devices and may promote wafer-scale integration of VC-based spin qubits for use in quantum computing devices.

公开(公告)号：US20190157393A1

公开(公告)日：2019-05-23

申请号：US16097592

申请日：2016-06-08

Applicant: Intel Corporation

Inventor： Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Zachary R. Yoscovits ,  James S. Clarke

IPC: H01L29/12 ,  H01L29/778 ,  H01L29/49 ,  H01L29/423 ,  H03K17/687 ,  H01L29/66 ,  H01L21/321 ,  H01L21/28 ,  H01L29/165

CPC classification number: H01L29/127 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/28088 ,  H01L21/3212 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/423 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66431 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/7613 ,  H01L29/778 ,  H01L29/7781 ,  H01L29/7782 ,  H03K17/687

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; and one or more gates disposed on the fin. In some such embodiments, the one or more gates may include first, second, and third gates. Spacers may be disposed on the sides of the first and second gates, such that a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate. The third gate may be disposed on the fin between the first and second gates and extend between the first and second spacers.

公开(公告)号：US20190044066A1

公开(公告)日：2019-02-07

申请号：US15928220

申请日：2018-03-22

Applicant: INTEL CORPORATION

Inventor： Nicole K. Thomas ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Hubert C. George ,  Jeanette M. Roberts ,  David J. Michalak ,  Roman Caudillo ,  Zachary R. Yoscovits ,  Lester Lampert ,  James S. Clarke

IPC: H01L49/00 ,  G02B6/12 ,  G06N99/00

CPC classification number: H01L49/006 ,  B82Y10/00 ,  B82Y20/00 ,  B82Y40/00 ,  G02B6/12004 ,  G02B2006/12078 ,  G02B2006/12142 ,  G06N10/00 ,  Y10S977/814 ,  Y10S977/933

Abstract: Embodiments of the present disclosure propose two methods for integrating vacancy centers (VCs) on semiconductor substrates for forming VC-based spin qubit devices. The first method is based on using a self-assembly process for integrating VC islands on a semiconductor substrate. The second method is based on using a buffer layer of a III-N semiconductor material over a semiconductor substrate, and then integrating VC islands in an insulating carbon-based material such as diamond that is either grown as a layer on the III-N buffer layer or grown in the openings formed in the III-N buffer layer. Integration of VC islands on semiconductor substrates typically used in semiconductor manufacturing according to any of these methods may provide a substantial improvement with respect to conventional approaches to building VC-based spin qubit devices and may promote wafer-scale integration of VC-based spin qubits for use in quantum computing devices.

公开(公告)号：US20190044049A1

公开(公告)日：2019-02-07

申请号：US15900674

申请日：2018-02-20

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Hubert C. George ,  Kanwaljit Singh ,  Jeanette M. Roberts ,  David J. Michalak ,  Roman Caudillo ,  Zachary R. Yoscovits ,  Lester Lampert ,  James S. Clarke ,  Willy Rachmady

IPC: H01L39/22 ,  H01L39/02 ,  H01L39/24 ,  H01L39/04 ,  G06N99/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate and an adjacent second gate above the quantum well stack; and a gate wall between the first gate and the second gate, wherein the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material.

公开(公告)号：US20190044048A1

公开(公告)日：2019-02-07

申请号：US15891518

申请日：2018-02-08

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  Lester Lampert ,  James S. Clarke ,  Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Kanwaljit Singh ,  Roman Caudillo

IPC: H01L39/14 ,  H01L39/22 ,  H01L29/12 ,  H01L29/15 ,  H01L29/423 ,  H01L29/40 ,  H01L39/24 ,  G06N99/00

CPC classification number: H01L39/146 ,  G06N10/00 ,  H01L23/445 ,  H01L23/46 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L25/16 ,  H01L29/127 ,  H01L29/151 ,  H01L29/401 ,  H01L29/42316 ,  H01L39/228 ,  H01L39/24 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Disclosed herein are fabrication techniques for providing metal gates in quantum devices, as well as related quantum devices. For example, in some embodiments, a method of manufacturing a quantum device may include providing a gate dielectric over a qubit device layer, providing over the gate dielectric a pattern of non-metallic elements referred to as “gate support elements,” and depositing a gate metal on sidewalls of the gate support elements to form a plurality of gates of the quantum device.

公开(公告)号：US20190044046A1

公开(公告)日：2019-02-07

申请号：US16011829

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Roman Caudillo ,  Zachary R. Yoscovits ,  Lester Lampert ,  David J. Michalak ,  Jeanette M. Roberts ,  Ravi Pillarisetty ,  Hubert C. George ,  Nicole K. Thomas ,  James S. Clarke

IPC: H01L39/02 ,  H01L27/18 ,  H01L39/04 ,  H01L39/22 ,  H01L39/24 ,  G06N99/00

CPC classification number: H01L39/025 ,  G06N10/00 ,  H01L27/18 ,  H01L39/045 ,  H01L39/223 ,  H01L39/2493

Abstract: Various embodiments of the present disclosure present quantum circuit assemblies implementing vertically-stacked parallel-plate capacitors. Such capacitors include first and second capacitor plates which are parallel to one another and separated from one another by a gap measured along a direction perpendicular to the qubit plane, i.e. measured vertically. Fabrication techniques for manufacturing such capacitors are also disclosed. Vertically-stacked parallel-plate capacitors may help increasing coherence times of qubits, facilitate use of three-dimensional and stacked designs for quantum circuit assemblies, and may be particularly advantageous for realizing device scalability and use of 300-millimeter fabrication processes.