公开(公告)号：US10915444B2

公开(公告)日：2021-02-09

申请号：US16234271

申请日：2018-12-27

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Sampath K. Ratnam ,  Ashutosh Malshe ,  Peter Sean Feeley

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/02

Abstract: A processing device in a memory system determines whether a first data block of a plurality of data blocks on the memory component satisfies a first threshold criterion pertaining to a first number of the plurality of data blocks having a lower amount of valid data than a remainder of the plurality of data blocks. Responsive to the first data block satisfying the first threshold criterion, the processing device determines whether the first data block satisfies a second threshold criterion pertaining to a second number of the plurality of data blocks having been written to more recently than the remainder of the plurality of data blocks. Responsive to the first data block satisfying the second threshold criterion, the processing device determines whether a rate of change of an amount of valid data on the first data block satisfies a third threshold criterion. Responsive to the rate of change satisfying the third threshold criterion, the processing device identifies the first data block as a candidate for garbage collection on the memory component.

公开(公告)号：US20210027846A1

公开(公告)日：2021-01-28

申请号：US17035149

申请日：2020-09-28

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Michael G. Miller ,  Sampath Ratnam ,  Xu Zhang ,  Jie Zhou

IPC: G11C16/26 ,  G06F11/10 ,  G06F11/07 ,  G06F11/22 ,  G06F12/02 ,  G11C7/06 ,  G11C16/34

Abstract: Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.

公开(公告)号：US20200371870A1

公开(公告)日：2020-11-26

申请号：US16989478

申请日：2020-08-10

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Xiangang Luo ,  Vamsi Pavan Ravaprolu ,  Ashutosh Malshe

IPC: G06F11/10 ,  G06F11/14

Abstract: A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group.

公开(公告)号：US20200371690A1

公开(公告)日：2020-11-26

申请号：US16947713

申请日：2020-08-13

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Sampath K. Ratnam ,  Harish R. Singidi ,  Ashutosh Malshe ,  Kishore Kumar Muchherla

IPC: G06F3/06

Abstract: A system includes a memory component and a processing device to determine an amount of data stored at a region of a memory component and determine, based on the amount of data stored in the region of the memory component. The processing device determines a frequency to perform an operation on one or more memory cells of the region of the memory component. The processing device performs the operation on the one or more memory cells at the frequency to maintain the one or more memory cells of the region of the memory component in a first state associated with a first error rate for data stored at the one or more memory cells. The first error rate is less than a second error rate associated with a second state of the one or more memory cells.

公开(公告)号：US10755793B2

公开(公告)日：2020-08-25

申请号：US15799655

申请日：2017-10-31

Applicant: Micron Technology, Inc.

Inventor： Harish Singidi ,  Scott Stoller ,  Jung Sheng Hoei ,  Ashutosh Malshe ,  Gianni Stephen Alsasua ,  Kishore Kumar Muchherla

IPC: G11C16/34 ,  G11C16/28 ,  G11C11/56 ,  G11C16/26 ,  G11C16/04

Abstract: NAND memory devices are described that utilize higher read-margin cell types to provide a more granular read disturb indicator without utilizing dummy cells. For example, a NAND architecture may have some cells that are configured as SLC or MLC cells. SLC or MLC cells have more read disturb margin—that is these cells can withstand more read disturb current leakage into the cell before a bit error occurs than TLC or QLC cells. These higher margin cells may serve as the read disturb indicator for a group of cells that have a comparatively lower read disturb margin. Since there are more pages of these higher margin cells than there are pages of dummy cells, these indicators may serve a smaller group of pages than the dummy pages. This reduces the time needed to complete a read disturb scan as fewer pages need to be scanned.

公开(公告)号：US10719271B2

公开(公告)日：2020-07-21

申请号：US16193126

申请日：2018-11-16

Applicant: Micron Technology, Inc.

Inventor： Gianni Stephen Alsasua ,  Karl D. Schuh ,  Ashutosh Malshe ,  Kishore Kumar Muchherla ,  Vamsi Pavan Rayaprolu ,  Sampath Ratnam ,  Harish Reddy Singidi ,  Renato Padilla, Jr.

IPC: G11C7/04 ,  G06F3/06 ,  G06F12/1009 ,  G11C16/34 ,  G11C16/26 ,  G11C16/04

Abstract: Various examples are directed to systems and methods of managing a memory device. The memory device may receive a read request describing a logical address at the memory device. The memory device may obtain a table entry associated with the logical address. The table entry comprises a physical address corresponding to the logical address and a write temperature data indicating a write temperature for the logical address. The memory device may determine a corrected threshold voltage for reading the physical address based at least in part on the write temperature data and read the physical address using the corrected threshold voltage.

公开(公告)号：US10672452B2

公开(公告)日：2020-06-02

申请号：US16138115

申请日：2018-09-21

Applicant: Micron Technology, Inc.

Inventor： Gianni Stephen Alsasua ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Sampath Ratnam ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Renato Padilla, Jr.

IPC: G11C7/00 ,  G11C11/406 ,  G06F13/16

Abstract: Devices and techniques for temperature informed memory refresh are described herein. Temperature data can be updated in response to a memory component write performed under an extreme temperature. Here, the write is performed on a memory component element in the memory component. The memory component element can be sorted above other memory component elements in the memory component based on the temperature data. Once sorted to the top of these memory component elements, a refresh can be performed the memory component element.

公开(公告)号：US10586602B2

公开(公告)日：2020-03-10

申请号：US16436567

申请日：2019-06-10

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi ,  Peter Sean Feeley ,  Sampath Ratnam ,  Kulachet Tanpairoj ,  Ting Luo

IPC: G11C7/00 ,  G11C16/26 ,  G11C16/04 ,  G11C16/28 ,  G11C16/34 ,  G11C29/02 ,  G11C16/24 ,  G11C16/08

Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.

公开(公告)号：US20200020407A1

公开(公告)日：2020-01-16

申请号：US16448502

申请日：2019-06-21

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Gianni Stephen Alsasua ,  Ashutosh Malshe ,  Sampath Ratnam ,  Gary F. Besinga ,  Michael G. Miller

IPC: G11C16/26

Abstract: Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.

公开(公告)号：US10365854B1

公开(公告)日：2019-07-30

申请号：US15924951

申请日：2018-03-19

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Peter Sean Feeley ,  Ashutosh Malshe ,  Sampath Ratnam ,  Harish Singidi ,  Vamsi Pavan Rayaprolu

IPC: G06F3/06

Abstract: A variety of applications can include apparatus and/or methods that include tracking data temperatures of logical block addresses for a memory device by operating multiple accumulators by one or more data temperature analyzers to count host writes to ranges of logical block addresses. Data temperature for data written by a host is a measure of how frequently data at a logical block address is overwritten. In various embodiments, tracking can include staggering the start of counting by each of the multiple accumulators to provide subsequent binning of logical block addresses bands into temperature zones, which can achieve better data segregation. Data having a logical block address received from a host can be routed to a block associated with a temperature zone based on the binning provided by the staggered operation of the multiple accumulators by one or more data temperature analyzers. Additional apparatus, systems, and methods are disclosed.