公开(公告)号：US20220300374A1

公开(公告)日：2022-09-22

申请号：US17648395

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Jonathan S. Parry ,  Deping He ,  Xiangang Luo ,  Reshmi Basu

IPC: G06F11/10

Abstract: Methods, systems, and devices for redundant array management techniques are described. A memory system may include a volatile memory device, a non-volatile memory device, and one or more redundant arrays of independent nodes. The memory system may include a first redundant array controller and a second redundant array controller of a redundant array of independent nodes. The memory system may receive a write command associated with writing data to a type of memory cell. Based on the type of memory cell, the memory system may generate parity data corresponding to the data using one or both of the first redundant array controller and the second redundant array controller. In some examples, the first redundant array controller may be configured to generate parity data associated with a first type of failure and the second redundant array controller may be configured to generate parity data associated with a second type of failure.

公开(公告)号：US11416143B2

公开(公告)日：2022-08-16

申请号：US17143558

申请日：2021-01-07

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu ,  Richard C. Murphy

IPC: G06F3/00 ,  G06F3/06

Abstract: Methods, systems, and apparatuses related to runtime selection of memory devices and storage devices in a disaggregated memory system are described. For example, a controller can be coupled to a plurality of memory device and a plurality of storage devices. The controller can receive signaling indicative of a memory request corresponding to execution of an application. Responsive to receiving the signaling indicative of the memory request, the controller can select a memory device or a storage device, or both, selecting from the plurality of memory devices or the plurality of storage devices, or both, to perform a memory operation associated with the memory request. Responsive to receiving the memory request and selecting the memory device or the storage device, or both, the controller can perform the memory operation using the selected memory device or the selected storage device, or both.

公开(公告)号：US20220214805A1

公开(公告)日：2022-07-07

申请号：US17143558

申请日：2021-01-07

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu ,  Richard C. Murphy

IPC: G06F3/06

Abstract: Methods, systems, and apparatuses related to runtime selection of memory devices and storage devices in a disaggregated memory system are described. For example, a controller can be coupled to a plurality of memory device and a plurality of storage devices. The controller can receive signaling indicative of a memory request corresponding to execution of an application. Responsive to receiving the signaling indicative of the memory request, the controller can select a memory device or a storage device, or both, selecting from the plurality of memory devices or the plurality of storage devices, or both, to perform a memory operation associated with the memory request. Responsive to receiving the memory request and selecting the memory device or the storage device, or both, the controller can perform the memory operation using the selected memory device or the selected storage device, or both.

公开(公告)号：US20220164301A1

公开(公告)日：2022-05-26

申请号：US17105053

申请日：2020-11-25

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu ,  Jonathan S. Parry

IPC: G06F13/16 ,  G06F1/12

Abstract: Methods, systems, and devices for status check using signaling are described. A memory system may receive ready signals from memory dies. The ready signal may indicate whether a memory die is available to receive a command. The memory system may generate an indicator of whether the memory die is available based on values of ready signals. The memory system may output the indicator to a controller over one or more pins based on generating the indicator.

公开(公告)号：US20220137980A1

公开(公告)日：2022-05-05

申请号：US17576546

申请日：2022-01-14

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu ,  Richard C. Murphy

IPC: G06F9/4401 ,  G06F11/14 ,  G11C11/56 ,  G06F12/02 ,  G06F11/10

Abstract: Systems, apparatuses, and methods related to configurable media structure are described. A memory device can be configured to boot up in a variety of configurations. The variety of configurations can include using the memory device for persistent memory storage, for non-persistent memory storage, etc. For instance, an apparatus can include a first memory array and a second memory array. The apparatus can include a memory controller coupled to the first memory array and the second memory array. The second memory array can be configured to store at least two boot images. The first memory array can be configured to operate based on which of the at least two boot images is used.

公开(公告)号：US11237841B2

公开(公告)日：2022-02-01

申请号：US16546416

申请日：2019-08-21

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu ,  Richard C. Murphy

IPC: G06F9/4401 ,  G06F11/14 ,  G11C11/56 ,  G06F12/02 ,  G06F11/10 ,  G11C7/20 ,  G11C16/20

Abstract: Systems, apparatuses, and methods related to configurable media structure are described. A memory device can be configured to boot up in a variety of configurations. The variety of configurations can include using the memory device for persistent memory storage, for non-persistent memory storage, etc. For instance, an apparatus can include a first memory array and a second memory array. The apparatus can include a memory controller coupled to the first memory array and the second memory array. The second memory array can be configured to store at least two boot images. The first memory array can be configured to operate based on which of the at least two boot images is used.

公开(公告)号：US20210278891A1

公开(公告)日：2021-09-09

申请号：US17322034

申请日：2021-05-17

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu

IPC: G06F1/3234 ,  G06F1/3225 ,  G06F9/50

Abstract: Systems, apparatuses, and methods related to thermal leveling are described. Thermal leveling can be performed on a host computing system as opposed to on a memory system. Thermal leveling can include operations performed by a host to control temperature characteristics and/or power consumption of a memory system. For instance, a host computing system can control temperature characteristics of multiple memory devices that are deployed in a memory system. In an example, a set of processing resources (e.g., a thermal leveling component) can be provided on a host. The set of processing resources can receive information corresponding to thermal characteristics of a memory device coupled to the host and control a thermal setting for the memory device based on the received thermal characteristics.

公开(公告)号：US20210248063A1

公开(公告)日：2021-08-12

申请号：US16786029

申请日：2020-02-10

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu ,  Richard Donald Maes, II ,  Katie Blomster Park ,  Robert J. Pintar ,  Gary A. Johnson

IPC: G06F12/02

Abstract: A method is described that includes receiving a write request with user data and a logical address and select a next address queue from a plurality of next address queues based on a reciprocal relationship between short-term usage information associated with the logical address and a set of characteristics of the selected next address queue. Each next address queue in the plurality of next address queues stores physical addresses that are designated to be used for fulfilling write requests. Further, a next physical address is removed from the selected next address queue and the user data of the write request is written to the next physical address in a memory device.

公开(公告)号：US10824502B2

公开(公告)日：2020-11-03

申请号：US16058813

申请日：2018-08-08

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu

IPC: G06F11/10 ,  G06F12/02 ,  G06F3/06 ,  G06F12/06

Abstract: Methods, apparatuses, and systems for error recovery in memory devices are described. A die-level redundancy scheme may be employed in which parity data associated with particular die may be stored. An example apparatus may include a printed circuit board and memory devices. Each memory device may be each disposed on a planar surface of the printed circuit board and may each include two or more memory die. The apparatus may also include multiple channels communicatively coupled to the two or more memory die and a memory controller. The memory controller may be communicatively coupled to the multiple channels and may deterministically maintain a redundancy scheme via data transmission through the multiple channels. The memory controller may also update memory operation information appended to the enhanced codeword in response to a memory operation request.

公开(公告)号：US20200285298A1

公开(公告)日：2020-09-10

申请号：US16296891

申请日：2019-03-08

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu

IPC: G06F1/3234 ,  G06F9/50 ,  G06F1/3225

Abstract: Systems, apparatuses, and methods related to thermal leveling are described. Thermal leveling can be performed on a host computing system as opposed to on a memory system. Thermal leveling can include operations performed by a host to control temperature characteristics and/or power consumption of a memory system. For instance, a host computing system can control temperature characteristics of multiple memory devices that are deployed in a memory system. In an example, a set of processing resources (e.g., a thermal leveling component) can be provided on a host. The set of processing resources can receive information corresponding to thermal characteristics of a memory device coupled to the host and control a thermal setting for the memory device based on the received thermal characteristics.