公开(公告)号：US20170279963A1

公开(公告)日：2017-09-28

申请号：US15619470

申请日：2017-06-10

Applicant: Millind Mittal

Inventor： Millind Mittal

IPC: H04M3/493 ,  H04M15/06

CPC classification number: H04M3/493 ,  H04M1/72552 ,  H04M1/72583 ,  H04M3/42382 ,  H04M3/4365 ,  H04M3/4931 ,  H04M3/5166 ,  H04M3/527 ,  H04M11/08 ,  H04M15/06 ,  H04M15/56 ,  H04M15/8083 ,  H04M15/8221 ,  H04M2201/42 ,  H04M2203/651

Abstract: A computerized method of terminating audio telephone calls that provides the other party with more information as to why the telephone call was terminated. This method, which is particularly useful for computerized smartphones equipped with voice and data channel communications methods, automatically provides the user with a variety of different informative text messages that can be selected by the user and sent to the other party at the time that a voice call is terminated.

公开(公告)号：US20130124834A1

公开(公告)日：2013-05-16

申请号：US13730848

申请日：2012-12-29

Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

公开(公告)号：US20130117538A1

公开(公告)日：2013-05-09

申请号：US13730839

申请日：2012-12-29

Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

公开(公告)号：US08396915B2

公开(公告)日：2013-03-12

申请号：US13603370

申请日：2012-09-04

Applicant: Alexander Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Carole Dulong ,  Eiichi Kowashi ,  Wolf C. Witt

Inventor： Alexander Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Carole Dulong ,  Eiichi Kowashi ,  Wolf C. Witt

IPC: G06F7/38

CPC classification number: G06F7/60 ,  G06F7/4812 ,  G06F7/49921 ,  G06F7/5324 ,  G06F7/5338 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30112 ,  G06F15/7817 ,  G06F17/10 ,  G06F17/147 ,  G06F17/16 ,  G06F2207/3828 ,  G06T1/20

Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

公开(公告)号：US08356020B2

公开(公告)日：2013-01-15

申请号：US12190692

申请日：2008-08-13

Applicant: Millind Mittal

Inventor： Millind Mittal

IPC: G06F7/00

CPC classification number: G06F17/30961 ,  Y10S707/99942 ,  Y10S707/99943

Abstract: A lookup is performed using multiple levels of compressed stride tables in a multi-bit Trie structure. An input lookup key is divided into several strides including a current stride of S bits. A valid entry in a current stride table is located by compressing the S bits to form a compressed index of D bits into the current stride table. A compression function logically combines the S bits to generate the D compressed index bits. An entry in a prior-level table points to the current stride table and has a field indicating which compression function and mask to use. Compression functions can include XOR, shifts, rotates, and multi-bit averaging. Rather than store all 2S entries, the current stride table is compressed to store only 2D entries. Ideally, the number of valid entries in the current stride table is between 2D−1 and 2D for maximum compression. Storage requirements are reduced.

Abstract translation: 在多位Trie结构中使用多级压缩步幅表进行查找。 输入查找键被分成包括S位的当前步幅的多个步骤。 通过压缩S位来形成当前步幅表中的有效条目，以形成D位的压缩索引到当前步幅表中。 压缩函数逻辑组合S位以产生D压缩索引位。 前一级表中的条目指向当前步幅表，并具有指示要使用的压缩函数和掩码的字段。 压缩功能可以包括XOR，移位，旋转和多位平均。 而不是存储所有2S条目，当前步幅表被压缩以仅存储2D条目。 理想情况下，当前步幅表中有效条目的数量在2D-1和2D之间用于最大压缩。 存储要求降低。

公开(公告)号：US20120331028A1

公开(公告)日：2012-12-27

申请号：US13603370

申请日：2012-09-04

Applicant: Alexander D. Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Carole Dulong ,  Eiichi Kowashi ,  Wolf Witt

Inventor： Alexander D. Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Carole Dulong ,  Eiichi Kowashi ,  Wolf Witt

IPC: G06F7/38

CPC classification number: G06F7/60 ,  G06F7/4812 ,  G06F7/49921 ,  G06F7/5324 ,  G06F7/5338 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30112 ,  G06F15/7817 ,  G06F17/10 ,  G06F17/147 ,  G06F17/16 ,  G06F2207/3828 ,  G06T1/20

Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

Abstract translation: 一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。 在一个实施例中，处理器耦合到存储器。 存储器中存储有第一打包数据和第二打包数据。 处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。 该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

公开(公告)号：US20120198210A1

公开(公告)日：2012-08-02

申请号：US13444090

申请日：2012-04-11

Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

Abstract: A processor. The processor includes a first register for storing a first packed data, a decoder, and a functional unit. The decoder has a control signal input. The control signal input is for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation. The second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder and the register. The functional unit is for performing the pack operation and the unpack operation using the first packed data. The processor also supports a move operation.

Abstract translation: 处理器 处理器包括用于存储第一打包数据的第一寄存器，解码器和功能单元。 解码器具有控制信号输入。 控制信号输入用于接收第一控制信号和第二控制信号。 第一控制信号用于指示包装操作。 第二控制信号用于指示解封装操作。 功能单元耦合到解码器和寄存器。 功能单元用于使用第一打包数据执行包操作和拆包操作。 处理器还支持移动操作。

公开(公告)号：US08185571B2

公开(公告)日：2012-05-22

申请号：US12409275

申请日：2009-03-23

Applicant: Alexander D. Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Carole Dulong ,  Eiichi Kowashi ,  Wolf Witt

Inventor： Alexander D. Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Carole Dulong ,  Eiichi Kowashi ,  Wolf Witt

IPC: G06F7/38

CPC classification number: G06F7/60 ,  G06F7/4812 ,  G06F7/49921 ,  G06F7/5324 ,  G06F7/5338 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30112 ,  G06F15/7817 ,  G06F17/10 ,  G06F17/147 ,  G06F17/16 ,  G06F2207/3828 ,  G06T1/20

Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

Abstract translation: 一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。 在一个实施例中，处理器耦合到存储器。 存储器中存储有第一打包数据和第二打包数据。 处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。 该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

公开(公告)号：US20120054616A1

公开(公告)日：2012-03-01

申请号：US13007025

申请日：2011-01-14

Applicant: Millind Mittal

Inventor： Millind Mittal

IPC: G06F3/00

CPC classification number: G06F17/30899 ,  H04L67/02 ,  H04N21/41407 ,  H04N21/42209 ,  H04N21/43637 ,  H04N21/6587

Abstract: Method of controlling playback of Internet web page video on remote or high quality video displays using a remote control device, such as a smart phone. The method runs a first client browser on the remote control device, which in turn sends commands to a proxy browser with a data buffer. In response to user commands from the remote control device, the proxy browser retrieves and buffers video and non-video web page data from Internet servers, and sends this data to the remote control device. Upon user command, the proxy browser also sends selected buffered data to a second client browser that is connected to the remote or high quality video display. Media player playback commands on the remote control are echoed to a second media player on the second client browser, resulting in good synchronization between devices. Various compression, IP address adjustment, and public key methods are also discussed.

Abstract translation: 使用诸如智能电话的遥控设备来控制远程或高质量视频显示器上的因特网网页视频回放的方法。 该方法在远程控制设备上运行第一个客户端浏览器，该客户端浏览器依次使用数据缓冲区将命令发送到代理浏览器。 响应于来自遥控设备的用户命令，代理浏览器从互联网服务器检索和缓冲视频和非视频网页数据，并将该数据发送到遥控设备。 根据用户命令，代理浏览器还将选定的缓冲数据发送到连接到远程或高质量视频显示器的第二客户端浏览器。 遥控器上的媒体播放器播放命令被回传到第二个客户端浏览器上的第二媒体播放器，导致设备之间的良好同步。 还讨论了各种压缩，IP地址调整和公钥方法。

公开(公告)号：US07966482B2

公开(公告)日：2011-06-21

申请号：US11451906

申请日：2006-06-12

Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

IPC: G06F9/315

CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed data element are received from the first source register. A third packed data element and a fourth packed data element are received from the second source register. The circuit packs packing a portion of each of the packed data elements into a destination register resulting with the portion from second packed data element adjacent to the portion from the first packed data element, and the portion from the fourth packed data element adjacent to the portion from the third packed data element.

Abstract translation: 一种装置包括指令解码器，第一和第二源寄存器和耦合到解码器的电路，用于从源寄存器接收压缩数据，并响应于解码器接收到的包指令对压缩数据进行打包。 从第一源寄存器接收第一打包数据元素和第二打包数据元素。 从第二源寄存器接收第三压缩数据元素和第四打包数据元素。 所述电路包装将每个打包数据元素的一部分包装到目的地寄存器中，其结果是来自与来自第一打包数据元素的部分相邻的第二打包数据元素的部分，以及来自与该部分相邻的第四打包数据元素的部分 从第三个打包的数据元素。