公开(公告)号：US06515370B2

公开(公告)日：2003-02-04

申请号：US09180225

申请日：1999-04-22

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L2348

CPC classification number: H01L25/0657 ,  H01L23/3114 ,  H01L23/49575 ,  H01L23/525 ,  H01L23/562 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83101 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/00012

Abstract: An integrated type semiconductor device that is capable of reducing cost or improving the reliability of connecting semiconductor chips together or chips to a circuit board. One embodiment of such an integrated type semiconductor device comprises a first semiconductor device (10) having a semiconductor chip (12) with electrodes (16), a stress-relieving layer (14) prepared on the semiconductor chip (12), a wire (18) formed across the electrodes (16) and the stress-relieving layer (14), and solder balls (19) formed on the wire (18) over the stress-relieving layer (14); and a bare chip (20) as a second semiconductor device to be electrically connected to the first semiconductor device (10).

Abstract translation: 一种集成型半导体器件，其能够降低成本或提高将半导体芯片连接在一起或将芯片连接到电路板的可靠性。 这种集成型半导体器件的一个实施例包括具有电极（16）的半导体芯片（12）和在半导体芯片（12）上制备的应力消除层（14）的第一半导体器件（10） 18）形成在电极（16）和应力消除层（14）之间，以及形成在线（18）上的应力消除层（14）上的焊球（19）; 以及作为与第一半导体器件（10）电连接的第二半导体器件的裸芯片（20）。

公开(公告)号：US06482673B2

公开(公告)日：2002-11-19

申请号：US09091291

申请日：1998-06-16

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L2144

CPC classification number: H01L21/563 ,  H01L23/3107 ,  H01L23/3114 ,  H01L2224/73203 ,  H01L2924/01078 ,  H01L2924/01079

Abstract: This is a semiconductor device, a method of the same, a circuit board, and a flexible substrate that are easy to handle, enable quality assurance, and also enable batch connection of a flexible substrate to the electrodes of a semiconductor chip. A gap preservation member 16 is provided on a surface, of a flexible substrate 12, on which connection portions 24 to electrodes 14 of a semiconductor chip 10 are disposed. The semiconductor chip 10 and the flexible substrate 12 are arranged in a state in which the gap preservation member 16 is interposed therebetween. The connection portions 24 provided on the flexible substrate 12 are connected to the electrodes 14 of the semiconductor chip 10, and a molding material is injected to provide a stress absorption layer 26.

Abstract translation: 这是一种易于处理的半导体器件，其方法，电路板和柔性基板，能够进行质量保证，并且还能够将柔性基板批量连接到半导体芯片的电极。 在柔性基板12的表面上设置有间隙保持部件16，半导体芯片10的连接部24〜电极14设置在该基板上。 半导体芯片10和柔性基板12配置成间隙保持部件16插入其间的状态。 设置在柔性基板12上的连接部分24连接到半导体芯片10的电极14，并且注入模塑材料以提供应力吸收层26。

公开(公告)号：US06472726B1

公开(公告)日：2002-10-29

申请号：US09509403

申请日：2000-07-07

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L2352

CPC classification number: H01L24/83 ,  H01L23/4985 ,  H01L24/27 ,  H01L24/29 ,  H01L24/81 ,  H01L24/97 ,  H01L2223/54473 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/189 ,  H05K3/323 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/05624

Abstract: A semiconductor device and method for fabricating a semiconductor device. Semiconductor chips are affixed by an adhesive to a tape carrier on which bonding portions are formed in a matrix. Electrodes formed on the semiconductor chips are electrically connected to the bonding portions. The tape carrier is then divided into individual units for each of the semiconductor chips.

Abstract translation: 一种用于制造半导体器件的半导体器件和方法。 半导体芯片通过粘合剂固定到其上以基体形成结合部分的带载体。 形成在半导体芯片上的电极电连接到接合部分。 然后将带载体分成用于每个半导体芯片的单独的单元。

公开(公告)号：US06410364B1

公开(公告)日：2002-06-25

申请号：US09555141

申请日：2000-05-25

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L2144

CPC classification number: H01L21/563 ,  H01L23/49816 ,  H01L24/29 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07811 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A semiconductor device comprises: a support member (20) on which a land (24) is formed; a semiconductor chip (10) having a bump for an electrode (12) that is disposed on the land (24), and to be bonded face-down to a support member (20); and resin (30) which is provided as an adhesive between the semiconductor chip (10) and the support member (20), which is allowed to contract on hardening, and which causes pressure-bonding between the land (24) and the bump (12) by the stress due to this hardening contraction. The stress therein is partially absorbed by elastic deformation of at least the support member (20).

Abstract translation: 一种半导体器件包括：形成有焊盘（24）的支撑部件（20）; 半导体芯片（10），其具有设置在所述焊盘（24）上的用于电极（12）的突起，并且被正面朝下地接合到支撑部件（20）; 以及树脂（30），其在所述半导体芯片（10）和所述支撑构件（20）之间作为粘合剂设置，所述树脂（30）在硬化时允许收缩，并且导致所述焊盘（24）和所述凸块之间的压接 12）由于这种硬化收缩引起的应力。 其中的应力部分地被至少支撑构件（20）的弹性变形吸收。

公开(公告)号：US06335563B1

公开(公告)日：2002-01-01

申请号：US09347519

申请日：1999-07-06

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L2358

CPC classification number: H01L24/83 ,  H01L23/4985 ,  H01L24/29 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device comprising a flexible substrate having an interconnecting pattern, an anisotropic conductive material arranged on a surface of the flexible substrate on which the interconnecting pattern is provided, a semiconductor chip provided with electrodes connected to the interconnecting pattern through the anisotropic conductive material, and a support member which is applied to the flexible substrate and secures the flatness. The anisotropic conductive material is provided so as to extend outside the semiconductor chip, and the support member is bonded to the flexible substrate via the anisotropic conductive material.

Abstract translation: 一种半导体器件，包括具有互连图案的柔性衬底，布置在其上设置有互连图案的柔性衬底的表面上的各向异性导电材料，设置有通过各向异性导电材料连接到互连图案的电极的半导体芯片，以及 支撑构件，其被施加到柔性基板并确保平坦度。 各向异性导电材料被设置成延伸到半导体芯片的外部，并且支撑构件经由各向异性导电材料结合到柔性基板。

公开(公告)号：US06333565B1

公开(公告)日：2001-12-25

申请号：US09272244

申请日：1999-03-19

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L2348

CPC classification number: H01L23/3107 ,  H01L23/3114 ,  H01L23/49816 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0401 ,  H01L2224/051 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A semiconductor device comprising: a semiconductor element having a plurality of electrodes; a passivation film formed on the semiconductor element in a region avoiding at least a part of each of the electrodes; a conductive foil provided at a given spacing from the surface on which the passivation film is formed; an external electrodes formed on the conductive foil; intermediate layer formed between the passivation film and the conductive foil to support the conductive foil; and wires electrically connecting the electrodes to the conductive foil; wherein a depression tapered in a direction from the conductive foil to the passivation film if formed under a part of the conductive foil that includes the connection with the external electrodes.

Abstract translation: 一种半导体器件，包括：具有多个电极的半导体元件; 在避免每个电极的至少一部分的区域中形成在半导体元件上的钝化膜; 以与形成有钝化膜的表面成一定距离设置的导电箔; 形成在导电箔上的外部电极; 形成在钝化膜和导电箔之间的中间层以支撑导电箔; 以及将电极与导电箔电连接的导线; 如果形成在包括与外部电极的连接的导电箔的一部分下方，则在从导电箔到钝化膜的方向上渐缩的凹陷。

公开(公告)号：US06274405B1

公开(公告)日：2001-08-14

申请号：US09077804

申请日：1998-06-15

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L2328

CPC classification number: H01L24/86 ,  H01L23/49572 ,  H01L23/4985 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/351 ,  H05K3/241 ,  H01L2924/00

Abstract: This is a semiconductor device made by using a film carrier tape and method of making the same, wherein the package size is close to the chip size and connection portions for electrodes of a semiconductor chip are not exposed. Electroplating is performed in a state where connection leads 24, plating leads 26 and plating electrodes 28 are all conductive, the connection leads being are formed within a region to be filled with a molding material 36 and being connected to electrodes 42 of a semiconductor chip 40 and pad portions 22, the plating leads 26 being connected to the connection leads 24, and plating electrodes 28 being connected to the plating leads 26. The connection portions 29 are punched out into the region to be filled with the molding material, the connection leads 24 and the electrodes 42 are connected, and the molding material 36 is poured in. The end surfaces of the connection leads 24 that are exposed from the holes 32 are also covered by the molding material 36 so as not to be exposed.

公开(公告)号：US06249046B1

公开(公告)日：2001-06-19

申请号：US09155985

申请日：1999-02-18

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L2352

CPC classification number: H01L24/50 ,  H01L23/49572 ,  H01L23/49816 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A semiconductor device for surface-mounting that allows of easy mounting. It comprises a semiconductor element 16, an insulating film 12, a wiring pattern 20 formed on a first surface of the insulating film 12 and connected to the semiconductor element 16, bumps 14 formed on the reverse side of the wiring pattern 20 and projecting through holes 12a formed in the insulating film 12 to the second surface of the insulating film 12, and a support plate 24 being electrically conductive and adhered so as to cover the wiring pattern 20 on the first surface of the insulating film 12 and acting as a planarity maintaining member. The support plate 24 is connected to a constant potential portion of the wiring pattern 20.

Abstract translation: 一种用于表面安装的半导体器件，可轻松安装。 其包括半导体元件16，绝缘膜12，形成在绝缘膜12的第一表面上并连接到半导体元件16的布线图案20，形成在布线图案20的背面上的凸起14和突出的通孔 12a形成在绝缘膜12的绝缘膜12的第二表面上，并且支撑板24是导电和粘附的，以覆盖绝缘膜12的第一表面上的布线图案20，并且作为平面保持 会员。 支撑板24连接到布线图案20的恒定电位部分。

公开(公告)号：US06144507A

公开(公告)日：2000-11-07

申请号：US214677

申请日：1999-03-18

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L25/16 ,  H01L21/60 ,  H01L31/02 ,  H01L31/0203 ,  G02B7/02

CPC classification number: H01L24/81 ,  H01L31/02002 ,  H01L31/0203 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/3025

Abstract: A new mounting technology allows an optical transducer or semiconductor device to be mounted on a printed wiring board at high density, simply, and at low cost. When a sealed assembly is mounted on a printed wiring board (400), an opening portion (340) is provided in a portion of the printed wiring board. Conductive junction portions (360b and 360c) are provided on the surface of a base member (100). Then, the mounting is carried out by face-down bonding. The opening portion is provided in the printed wiring board, so that at least a portion of a sealing member of the sealed assembly is inserted in the opening portion. Such a structure makes face-down bonding possible, since the thickness of the sealing member of the sealed assembly and the thickness of the printed wiring board are adjusted by inserting the sealed assembly into the printed wiring board.

Abstract translation: PCT No.PCT / JP97 / 02304 Sec。 371 1999年3月18日 102（e）1999年3月18日PCT PCT 1997年7月3日PCT公布。 公开号WO98 / 03990 日期1998年1月29日新的安装技术允许光学传感器或半导体器件以高密度，简单且低成本地安装在印刷电路板上。 当密封组件安装在印刷电路板（400）上时，在印刷电路板的一部分中设置开口部分（340）。 导电接合部分（360b和360c）设置在基体（100）的表面上。 然后，通过面朝下的粘结进行安装。 开口部设置在印刷布线板中，使得密封组件的密封构件的至少一部分插入开口部。 由于通过将密封组件插入印刷电路板来调节密封组件的密封构件的厚度和印刷电路板的厚度，因此这种结构使得可以进行面朝下的接合。

公开(公告)号：US5970320A

公开(公告)日：1999-10-19

申请号：US833311

申请日：1997-04-04

Applicant: Yasuo Yamasaki ,  Norikata Hama ,  Munenori Kurasawa ,  Nobuaki Hashimoto

Inventor： Yasuo Yamasaki ,  Norikata Hama ,  Munenori Kurasawa ,  Nobuaki Hashimoto

IPC: H01L23/31 ,  H01L23/433 ,  H01L23/495 ,  H01L23/498 ,  H01L21/56 ,  H01L21/58 ,  H01L21/60

CPC classification number: H01L23/3135 ,  H01L23/4334 ,  H01L23/49524 ,  H01L23/49572 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1532 ,  H01L2924/19105

Abstract: A semiconductor device comprises an electrically insulating film having a device hole; a plurality of groups of leads, each group including of a large number of leads arranged in a predetermined pattern, in a plurality of lead formation regions on the surface of the film; an integrated circuit chip positioned within the device hole and with electrodes connected to inner lead portions of the leads; and a resin sealing portion that seals in at least the integrated circuit chip, the film, and the lead groups. The film comprises a first group of aperture portions including of aperture portions provided in regions outside the lead formation regions and a second group of aperture portions consisting of a plurality of aperture portions provided in the lead formation regions.

Abstract translation: 半导体器件包括具有器件孔的电绝缘膜; 在膜的表面上的多个引线形成区域中的多组引线，每组包括以预定图案布置的大量引线; 集成电路芯片，其位于所述器件孔内并且具有连接到所述引线的内引线部分的电极; 以及密封至少集成电路芯片，膜和引线组的树脂密封部。 该膜包括第一组开口部分，其包括设置在引线形成区域外的区域中的开口部分和由设置在引线形成区域中的多个开口部分组成的第二组开口部分。