公开(公告)号：US20200152609A1

公开(公告)日：2020-05-14

申请号：US16741749

申请日：2020-01-14

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: A method of fabricating a package structure including at least the following steps is provided. A carrier is provided. A first package is formed on the carrier. The first package is formed by at least the following steps. A first redistribution layer is formed on the carrier, wherein the first redistribution layer has a first surface and a second surface opposite to the first surface. A semiconductor die is bonded on the first surface of the first redistribution layer. The semiconductor die is electrically connected to the first redistribution layer through a plurality of conductive wires. An insulating material is formed to encapsulate the semiconductor die and the plurality of conductive wires. A thinning process is performed to obtain an insulating encapsulant by reducing a thickness of the insulating material until a portion of each of the conductive wires is removed to form a plurality of conductive wire segments, wherein the semiconductor die is electrically insulated from the first redistribution layer after the thinning process. A second redistribution layer is formed on a top surface of the insulating encapsulant, and over the semiconductor die. The second redistribution layer is electrically connected to the first redistribution layer and to the semiconductor die by the plurality of conductive wire segments.

公开(公告)号：US10593647B2

公开(公告)日：2020-03-17

申请号：US16019551

申请日：2018-06-27

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00 ,  H01L23/31

Abstract: A package structure including first and second packages is provided. The first package includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, and a plurality of conductive wire segments. The semiconductor die has an active surface and a back surface. The insulating encapsulant encapsulates the semiconductor die. The first redistribution layer is disposed on the back surface of the semiconductor die and a bottom surface of the insulating encapsulant. The first redistribution layer has a first surface and a second surface opposite to the first surface. The second redistribution layer is disposed on the active surface of the semiconductor die. The plurality of conductive wire segments electrically connects the semiconductor die to the second redistribution layer and the first redistribution layer to the second redistribution layer. The second package is stacked on the second surface of the first redistribution layer over the first package.

公开(公告)号：US20200035614A1

公开(公告)日：2020-01-30

申请号：US16048351

申请日：2018-07-30

Applicant: Powertech Technology Inc.

Inventor： Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L23/552 ,  H01L23/13 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/367 ,  H01L21/683

Abstract: A package structure including a frame structure, a die, an encapsulant, and a redistribution structure is provided. The frame structure has a cavity. The die is disposed in the cavity. The die has an active surface, a rear surface opposite to the active surface, a plurality of lateral sides connecting the active surface and the rear surface, and a plurality of connection pads disposed on the active surface. The encapsulant encapsulates at least a portion of the frame structure and lateral sides of the die. The redistribution structure is disposed on the encapsulant and the active surface of the die. The connection pads are directly in contact with the redistribution structure.

公开(公告)号：US10381278B2

公开(公告)日：2019-08-13

申请号：US15705250

申请日：2017-09-14

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Nan-Chun Lin

IPC: H01L21/26 ,  G01R31/02 ,  G01R31/28 ,  H01L23/00 ,  H01L21/66

Abstract: A testing method of a packaging process includes following steps. A substrate is provided. A circuit structure is formed on the substrate. The circuit structure includes a real unit area and a dummy side rail surrounding the real unit area, and a plurality of first circuit patterns is disposed on the real unit area. A second circuit pattern is formed on the dummy side rail, and the second circuit pattern emulates the configurations of at least a portion of the first circuit patterns for operating a simulation test. In addition, a packaging structure adapted for a testing process is also mentioned.

公开(公告)号：US20190189494A1

公开(公告)日：2019-06-20

申请号：US15847936

申请日：2017-12-20

Applicant: Powertech Technology Inc.

Inventor： Hsing-Te Chung ,  Yong-Cheng Chuang ,  Kuo-Ting Lin ,  Nan-Chun Lin

IPC: H01L21/683 ,  H01L23/498 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/48 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68309 ,  H01L2221/68368 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2924/19105 ,  H01L2924/19106

Abstract: A manufacturing method of a package structure is provided. The method includes the following steps. A package panel is provided. The package panel includes a first encapsulation, a plurality of first integrated circuit components and a plurality of redistribution circuit patterns electrically connected to the first integrated circuit components, the first integrated circuit components are encapsulated by the first encapsulation, and the redistribution circuit patterns are distributed on the first encapsulation and the first integrated circuit components. The first encapsulation of the package panel is cut to form a plurality of singulated package strips. One of the singulated package strips is attached onto an attachment region of a substrate. The substrate includes at least one tooling hole distributed outside of the attachment region. The package process is performed over the singulated package strip with the substrate affixed through the tooling hole to form the package structure.

公开(公告)号：US20190051626A1

公开(公告)日：2019-02-14

申请号：US16164811

申请日：2018-10-19

Applicant: Powertech Technology Inc.

Inventor： Li-Chih Fang ,  Hung-Hsin Hsu ,  Nan-Chun Lin ,  Shang-Yu Chang Chien

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/538 ,  H01L23/498

Abstract: A manufacturing method of a chip package structure includes: dicing a wafer to separate chips formed thereon; mounting the chips on a carrier, wherein an active surface and pads of each chip are buried in an adhesive layer disposed on the carrier, and a top surface of the adhesive layer between the chips is bulged away from the carrier; forming an encapsulant to encapsulate the chips and cover the adhesive layer, wherein the encapsulant has a concave surface covering the top surface of the adhesive layer and a back surface opposite to the concave surface; removing the carrier and the adhesive layer; forming a first dielectric layer to cover the concave surface and the active surface; forming a patterned circuit layer on the first dielectric layer, to electrically connect to the pads through openings in the first dielectric layer; and forming a second dielectric layer on the patterned circuit layer.

公开(公告)号：US20190013214A1

公开(公告)日：2019-01-10

申请号：US15644831

申请日：2017-07-10

Applicant: Powertech Technology Inc.

Inventor： Han-Wen Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Nan-Chun Lin

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/065

Abstract: A manufacturing method of a package structure is described. The method includes at least the following steps. A carrier is provided. A semiconductor die and a sacrificial structure are disposed on the carrier. The semiconductor die is electrically connected to the bonding pads on the sacrificial structure through a plurality of conductive wires. As encapsulant is formed on the carrier to encapsulate the semiconductor die, the sacrificial structure and the conductive wires. The carrier is debonded, and at least a portion of the sacrificial structure is removed through a thinning process. A redistribution layer is formed on the semiconductor die and the encapsulant. The redistribution layer is electrically connected to the semiconductor die through the conductive wires.

公开(公告)号：US10163834B2

公开(公告)日：2018-12-25

申请号：US15600804

申请日：2017-05-22

Applicant: Powertech Technology Inc.

Inventor： Li-Chih Fang ,  Hung-Hsin Hsu ,  Nan-Chun Lin ,  Shang-Yu Chang Chien

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/498 ,  H01L23/538

Abstract: A chip package structure includes a chip, an encapsulant, a dielectric layer and a patterned circuit layer. The chip includes an active surface and a plurality of pads disposed on the active surface. The encapsulant encapsulates the chip and exposes active surface, wherein the encapsulant includes a concave surface and a back surface opposite to the concave surface, the concave surface exposes the active surface and is dented toward the back surface. The dielectric layer covers the concave surface and the active surface and includes a plurality of openings exposing the pads, wherein the opening includes a slanted side surface and the angle between the slanted side surface and the active surface is an acute angle. The patterned circuit layer is disposed on the dielectric layer and electrically connected to the pads through the openings.

公开(公告)号：US20180350708A1

公开(公告)日：2018-12-06

申请号：US15614617

申请日：2017-06-06

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/48 ,  H01L23/538 ,  H01L21/768

Abstract: A package structure includes a redistribution structure, a die, an insulation encapsulation, a protection layer, and a plurality of conductive terminals. The redistribution structure has a first surface and a second surface opposite to the first surface. The die is electrically connected to the redistribution structure. The die has an active surface, a rear surface opposite to the active surface, and lateral sides between the active surface and the rear surface. The insulation encapsulation encapsulates lateral sides of the die and the first surface of the redistribution structure. The protection layer is disposed on the rear surface of the die and the insulation encapsulation. The conductive terminals are formed on the second surface of the redistribution structure.

公开(公告)号：US20180301352A1

公开(公告)日：2018-10-18

申请号：US15603475

申请日：2017-05-24

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Hung-Hsin Hsu ,  Nan-Chun Lin ,  Shang-Yu Chang Chien

IPC: H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L21/4857 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/3025 ,  H01L2924/3511

Abstract: A chip packaging method includes forming a first redistribution layer and a first dielectric layer on a first temporary carrier to generate a plurality of first conductive interfaces close to the first temporary carrier, each pair of neighboring first conductive interfaces having a first pitch; forming a second dielectric layer on a first portion of the first redistribution layer and the first dielectric layer so as to cover the first portion of the first redistribution layer and expose a second portion; and forming a second redistribution layer and a third dielectric layer over the second dielectric layer to generate a plurality of second conductive interfaces. A circuitry being formed by at least the first redistribution layer and the second redistribution layer and each pair of neighboring second conductive interfaces has a second pitch larger than the first pitch.