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公开(公告)号:US20210376810A1
公开(公告)日:2021-12-02
申请号:US16884891
申请日:2020-05-27
Applicant: QUALCOMM Incorporated
Inventor: Jonghae KIM , Je-Hsiung LAN , Ranadeep DUTTA , Milind SHAH , Periannan CHIDAMBARAM
IPC: H03H9/05 , H01L41/053 , H01L41/047 , H03H9/145 , H01L25/04 , H03H9/64 , H01L41/23 , H03H3/02 , H03H9/02
Abstract: A package that includes a first filter comprising a first polymer, a substrate cap, a second filter comprising a second polymer frame, at least one interconnect, an encapsulation layer and a plurality of through encapsulation vias. The substrate cap is coupled to the first polymer frame such that a first void is formed between the substrate cap and the first filter. The second polymer frame is coupled to the substrate cap such that a second void is formed between the substrate cap and the second filter. The at least one interconnect is coupled to the first filter and the second filter. The encapsulation layer encapsulates the first filter, the substrate cap, the second filter, and the at least one interconnect. The plurality of through encapsulation vias coupled to the first filter.
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公开(公告)号:US20210375712A1
公开(公告)日:2021-12-02
申请号:US16883812
申请日:2020-05-26
Applicant: QUALCOMM Incorporated
Inventor: Aniket PATIL , Hong Bok WE , Jonghae KIM
IPC: H01L23/367 , H01L21/48 , H01L21/3065 , H01L23/373
Abstract: A semiconductor device includes a die having one or more trenches on a back side of the die. The semiconductor device also includes a layer of thermally conductive material deposited on the back side of the die to fill the one or more trenches to form one or more plated trenches. The size (e.g., surface area or thickness (Z-height)) or location of the plated trenches may be determined based on one or more heat generating elements such as logic devices (CPU or GPU, for example) on an active side of the die. The thermally conductive material, which may be a metal such as copper (Cu) or silver (Ag), has a heat dissipation coefficient that is greater than a heat dissipation coefficient of a substrate of the die.
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公开(公告)号:US20210327873A1
公开(公告)日:2021-10-21
申请号:US16854313
申请日:2020-04-21
Applicant: QUALCOMM Incorporated
Inventor: Je-Hsiung LAN , Ranadeep DUTTA , Jonghae KIM
IPC: H01L27/06 , H03F3/213 , H01L29/778 , H01L29/20 , H01L29/66
Abstract: A 3D integrated circuit (3D IC) chip is described. The 3D IC chip includes a die having a compound semiconductor high electron mobility transistor (HEMT) active device. The compound semiconductor HEMT active device is composed of compound semiconductor layers on a single crystal, compound semiconductor layer. The 3D IC chip also includes an acoustic device integrated in the single crystal, compound semiconductor layer. The 3D IC chip further includes a passive device integrated in back-end-of-line layers of the die on the single crystal, compound semiconductor layer.
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公开(公告)号:US20210280540A1
公开(公告)日:2021-09-09
申请号:US16812882
申请日:2020-03-09
Applicant: QUALCOMM Incorporated
Inventor: Jonghae KIM , Milind SHAH , Periannan CHIDAMBARAM
IPC: H01L23/00 , H01L23/31 , H01L23/532 , H01L23/64 , H01L21/56
Abstract: A device that includes a first package and a second package coupled to the first package. The first package includes a first integrated device, a first encapsulation layer encapsulating the first integrated device, a plurality of vias traveling through the first encapsulation layer, a first redistribution portion comprising a first plurality of redistribution interconnects, wherein the first redistribution portion is coupled to the first encapsulation layer, and a first plurality of contacts coupled to the first integrated device. The second package includes a passive device, a second encapsulation layer encapsulating the passive device, a second redistribution portion comprising a second plurality of redistribution interconnects, wherein the second redistribution portion is coupled to the passive device and the second encapsulation layer, and a second plurality of contacts coupled to the passive device, wherein the second plurality of contacts is coupled to the first plurality of contacts from the first package.
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95.
公开(公告)号:US20210242353A1
公开(公告)日:2021-08-05
申请号:US16782865
申请日:2020-02-05
Applicant: QUALCOMM Incorporated
Inventor: Jonghae KIM , Periannan CHIDAMBARAM
IPC: H01L29/94 , H01L29/66 , H01L21/768 , H01L27/08 , H01L23/522
Abstract: Certain aspects of the present disclosure generally relate to a capacitive element. One example capacitive element generally includes a substrate, a plurality of trench capacitors, an electrically conductive via, a first electrically conductive contact, and a second electrically conductive contact. The trench capacitors intersect the substrate. The electrically conductive via intersects the substrate and is disposed adjacent to at least one of the trench capacitors. The first electrically conductive contact is disposed above the substrate, and the second electrically conductive contact is disposed below the substrate and electrically coupled to the plurality of trench capacitors through the electrically conductive via.
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公开(公告)号:US20210104447A1
公开(公告)日:2021-04-08
申请号:US16592471
申请日:2019-10-03
Applicant: QUALCOMM Incorporated
Inventor: Jonghae KIM , Je-Hsiung LAN , Ranadeep DUTTA
IPC: H01L23/367 , H01L27/12 , H01L23/552 , H01L23/373 , H01L23/00 , H01L23/48 , H01L21/56
Abstract: Active devices in an integrated circuit (IC) die package, such as in a radio frequency front end (RFFE) package can generate significant amount of heat. This problem can become acute especially as the operating frequency is high such as in 5G NR. Also, electromagnetic interference issues can arise in such packages. One or more techniques to mitigate thermal and electrical interference issues in IC die packages are presented.
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公开(公告)号:US20210098567A1
公开(公告)日:2021-04-01
申请号:US16798161
申请日:2020-02-21
Applicant: QUALCOMM Incorporated
Inventor: Jonghae KIM , Milind SHAH , Periannan CHIDAMBARAM
IPC: H01L49/02 , H01L23/498 , H01L23/48 , H01L23/31 , H01L25/065
Abstract: A package that includes a substrate, an integrated device coupled to the substrate, and a capacitor structure located between the substrate and the integrated device. The capacitor structure includes a capacitor substrate comprising a first trench, a first electrically conductive layer located in the first trench, a dielectric layer located over the first electrically conductive layer, and a second electrically conductive layer located over the dielectric layer. The first electrically conductive layer over the first trench, the dielectric layer and the second electrically conductive layer are configured as a first capacitor.
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公开(公告)号:US20190356294A1
公开(公告)日:2019-11-21
申请号:US15982655
申请日:2018-05-17
Applicant: QUALCOMM Incorporated
Inventor: Nosun PARK , Changhan Hobie YUN , Jonghae KIM , Niranjan Sunil MUDAKATTE , Xiaoju YU , Wei-Chuan CHEN
IPC: H03H7/01 , H03H1/00 , H03H3/00 , H01F27/40 , H01L49/02 , H01L27/01 , H01L23/29 , H01L21/56 , H01L23/31 , H01L23/00 , H01L21/683 , H01L25/16
Abstract: A three-dimensional (3D) solenoid structure includes a first inductor portion having a first surface and a second surface opposite the first surface. The 3D solenoid structure further includes a first capacitor portion, a first inductor pillar, at least one capacitor pillar, a second inductor portion, a second inductor pillar and a first inductor bonding interface. The first inductor pillar is coupled to the first surface of the first inductor portion. The capacitor pillar(s) is coupled to the first capacitor portion. The second inductor portion includes a first surface and a second surface opposite the first surface. The second inductor pillar is coupled to the first surface of the second inductor portion. The first inductor bonding interface, between the first inductor pillar and the second inductor pillar, couples together the first inductor portion and the second inductor portion.
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公开(公告)号:US20170372831A1
公开(公告)日:2017-12-28
申请号:US15192802
申请日:2016-06-24
Applicant: QUALCOMM Incorporated
Inventor: Mario Francisco VELEZ , Daeik Daniel KIM , Niranjan Sunil MUDAKATTE , David Francis BERDY , Changhan Hobie YUN , Jonghae KIM , Chengjie ZUO , Yunfei MA , Robert Paul MIKULKA
CPC classification number: H01F41/041 , H01F17/0013 , H01F17/0033 , H01F2017/002 , H01L23/3128 , H01L23/645 , H01L24/19 , H01L24/24 , H01L24/96 , H01L2224/023 , H01L2224/12105 , H01L2224/24195 , H01L2924/1206 , H01L2924/18162 , H01L2924/19042 , H01L2924/19105
Abstract: Disclosed is an apparatus including a plurality of vias each having a defined shape, wherein each of the plurality of vias includes a first two-dimensional conductive layer plated on a first side of a substrate, the first two-dimensional conductive layer having the defined shape, a second two-dimensional conductive layer plated on a second side of the substrate, the second two-dimensional conductive layer having the defined shape, and a via conductively coupling the first two-dimensional conductive layer to the second two-dimensional conductive layer. The apparatus further includes a plurality of interconnects configured to conductively couple the plurality of vias, wherein the first two-dimensional conductive layer and the second two-dimensional conductive layer of each of the plurality of vias are perpendicular to the plurality of interconnects.
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公开(公告)号:US20170221846A1
公开(公告)日:2017-08-03
申请号:US15077869
申请日:2016-03-22
Applicant: QUALCOMM Incorporated
Inventor: Daeik Daniel KIM , Mario Francisco VELEZ , Changhan Hobie YUN , Chengjie ZUO , David Francis BERDY , Jonghae KIM , Niranjan Sunil MUDAKATTE
IPC: H01L23/00
CPC classification number: H01L24/11 , H01L23/15 , H01L23/3171 , H01L23/3192 , H01L23/49816 , H01L24/14 , H01L2224/11003 , H01L2224/11005 , H01L2224/1148 , H01L2224/1405 , H01L2224/14104 , H01L2224/145 , H05K1/0306 , H05K1/111 , H05K3/0052 , H05K2201/0154 , H05K2201/0195 , H05K2201/09845 , Y02P70/611
Abstract: A conductive bump assembly may include a passive substrate. The conductive bump assembly may also include a conductive bump pad supported by the passive substrate and surrounded by a first passivation layer opening. The conductive bump assembly may further include a second passivation layer opening on the passive substrate. The second passivation layer opening may be merged with the first passivation layer opening surrounding the conductive bump pad proximate an edge of the passive substrate. The conductive bump assembly may also include a conductive bump on the conductive bump pad.
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