公开(公告)号：US20240322791A1

公开(公告)日：2024-09-26

申请号：US18189779

申请日：2023-03-24

Applicant: QUALCOMM Incorporated

Inventor： Abhijeet PAUL ,  Jonghae KIM ,  Mishel MATLOUBIAN

IPC: H03H9/17 ,  H03H3/02

CPC classification number: H03H9/173 ,  H03H3/02 ,  H03H2003/021

Abstract: Disclosed are techniques for an integrated circuit (IC) that includes one or more transistors on a substrate and an interconnection structure on the one or more transistors. The interconnection structure includes a semiconductor structure embedded in the interconnection structure. In an aspect, the semiconductor structure includes a cavity structure, a piezoelectric layer over the cavity structure, an upper conductive structure on the piezoelectric layer, and a first contact structure on the upper conductive structure. In an aspect, the cavity structure includes a bottom that is a part of a first etch stop layer over a substrate, a top that is a part of a second etch stop layer over the first etch stop layer, one or more sidewalls connecting the bottom and the top of the cavity structure, and a cavity between the top and the bottom of the cavity structure and surrounded by the one or more sidewalls.

公开(公告)号：US20240321507A1

公开(公告)日：2024-09-26

申请号：US18189325

申请日：2023-03-24

Applicant: QUALCOMM Incorporated

Inventor： Kai LIU ,  Jui-Yi CHIU ,  Jonghae KIM

IPC: H01F27/28 ,  H01F27/24 ,  H01F27/29 ,  H01F27/32 ,  H01F41/069 ,  H01F41/10 ,  H01F41/12

CPC classification number: H01F27/2866 ,  H01F27/24 ,  H01F27/29 ,  H01F27/327 ,  H01F41/069 ,  H01F41/10 ,  H01F41/127

Abstract: Disclosed is a three-dimensional (3D) inductor with two-side bonding wires. The 3D inductor enables high inductance to be achieved, e.g., for integrated voltage regulators (IVR) and/or external voltage regulators (EVR). The inductance of the 3D inductor can be enhanced with magnetic molding compounds.

公开(公告)号：US20240105728A1

公开(公告)日：2024-03-28

申请号：US18472074

申请日：2023-09-21

Applicant: QUALCOMM Incorporated

Inventor： Qingqing LIANG ,  Haining YANG ,  Jonghae KIM ,  Periannan CHIDAMBARAM ,  George Pete IMTHURN ,  Jun YUAN ,  Giridhar NALLAPATI ,  Deepak SHARMA

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11853 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: Disclosed are standard cells, transistors, and methods for fabricating the same. In an aspect, a transistor includes a drain and a source each including a first drain/source silicide layer on a frontside surface of the drain/source and a second drain/source silicide layer on a backside surface of the drain/source. The first drain silicide layer is coupled to a first drain contact structure or the second drain silicide layer is coupled to a second drain contact structure. The first source silicide layer is coupled to a first source contact structure or the second source silicide layer is coupled to a second source contact structure. A gate structure is disposed between the source and the drain. A channel is at least partially enclosed by the gate structure and disposed between the source and the drain and is recessed from the backside surfaces of the source and drain.

公开(公告)号：US20240055356A1

公开(公告)日：2024-02-15

申请号：US18492402

申请日：2023-10-23

Applicant: QUALCOMM Incorporated

Inventor： Bharani CHAVA ,  Abinash ROY ,  Stanley Seungchul SONG ,  Jonghae KIM

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L23/5385 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227

Abstract: A package comprising a substrate; a first integrated device coupled to the substrate through at least a first plurality of solder interconnects; a second integrated device coupled to the substrate through at least a second plurality of solder interconnects; a first bridge coupled to the first integrated device and the second integrated device through at least a third plurality of solder interconnects, wherein the first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device, and wherein the first bridge is coupled to a top portion of the first integrated device and a top portion of the second integrated device, through at least the third plurality of solder interconnects; and a second bridge coupled to the first integrated device and the second integrated device through a fourth plurality of solder interconnects.

公开(公告)号：US20230246024A1

公开(公告)日：2023-08-03

申请号：US18298211

申请日：2023-04-10

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Milind SHAH ,  Periannan CHIDAMBARAM

IPC: H01L27/08 ,  H01L25/10 ,  H01L29/94 ,  H01L29/66 ,  H10B12/00

CPC classification number: H01L27/0805 ,  H01L28/90 ,  H01L25/105 ,  H01L29/945 ,  H01L29/66181 ,  H01L28/40 ,  H10B12/37 ,  H10B12/038 ,  H10B12/39

Abstract: Certain aspects of the present disclosure provide a capacitor assembly, a stacked capacitor assembly, an integrated circuit (IC) assembly comprising such a stacked capacitor assembly, and methods for fabricating the same. One exemplary capacitor assembly generally includes a first array of trench capacitors and a second array of trench capacitors. The second array of trench capacitors may be disposed adjacent to and electrically coupled to the first array of trench capacitors. Additionally, the second array of trench capacitors may be inverted with respect to the first array of trench capacitors.

公开(公告)号：US20230197554A1

公开(公告)日：2023-06-22

申请号：US17558508

申请日：2021-12-21

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung LAN ,  Jonghae KIM ,  Ranadeep DUTTA

IPC: H01L23/367 ,  H01L25/065 ,  H01L21/48 ,  H01L25/00

CPC classification number: H01L23/3677 ,  H01L25/0655 ,  H01L21/4871 ,  H01L25/50

Abstract: Disclosed are apparatuses and techniques for fabricating an apparatus including a semiconductor device. The semiconductor device may include: a die, a thermally conductive interface that includes a thermal bridge interposer (THBI) structure, and a substrate. The die is coupled to the substrate by the thermally conductive interface and at least a portion of the die is coupled to the substrate by the THBI structure.

公开(公告)号：US20230030569A1

公开(公告)日：2023-02-02

申请号：US17392005

申请日：2021-08-02

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Sang-June PARK ,  Periannan CHIDAMBARAM

IPC: H03H7/38 ,  H01P5/12 ,  H04B1/38

Abstract: An aspect relates to a signal power splitter/combiner including a first signal port; a first resistor; a first impedance transformer coupled in series with the first resistor between the first signal port and a first intermediate node; a second impedance transformer coupled between the first intermediate node and a second signal port; a third impedance transformer coupled between the first intermediate node and a third signal port; and a second resistor coupled between the second and third signal ports. The signal power splitter/combiner may further include a fourth impedance transformer coupled between the second impedance transformer and the second signal port, a fifth impedance transformer coupled between the third impedance transformer and the third signal port; and a third resistor coupled between a third intermediate nod.

公开(公告)号：US20220028758A1

公开(公告)日：2022-01-27

申请号：US16937426

申请日：2020-07-23

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Jonghae KIM ,  Periannan CHIDAMBARAM

IPC: H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: Disclosed is a semiconductor die with a through substrate via (TSV) structure having improved electrical characteristics suitable for backside power distribution networks (PDNs), and a method for making same. According to some aspects, a semiconductor die includes a substrate having a front side and a back side and includes a TSV extending from the back side of the substrate towards the front side of the substrate. The TSV includes a first portion extending from the back side of the substrate towards the front side of the substrate and having a first cross sectional area and a second portion extending from the first portion towards the front side of the substrate and having a second cross sectional area smaller than the first cross sectional area. A conductor is disposed within the TSV. According to some aspects, the first portion of the TSV is trench structure.

公开(公告)号：US20210296170A1

公开(公告)日：2021-09-23

申请号：US16820961

申请日：2020-03-17

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Jin-Su KO ,  Beomsup KIM ,  Periannan CHIDAMBARAM

IPC: H01L21/768 ,  H01L23/522 ,  H01L49/02

Abstract: Certain aspects of the present disclosure are generally directed to techniques and apparatus for adjusting capacitance in one or more metal-insulator-metal (MIM) capacitors in an effort to reduce capacitance variation between semiconductor devices and improve yield during fabrication. One example method for fabricating a semiconductor device generally includes measuring a capacitance value of a MIM capacitor of the semiconductor device, determining the measured capacitance value of the MIM capacitor is above a target capacitance value for the MIM capacitor, and selectively rupturing a set of connections in the MIM capacitor based on the measured capacitance value. Selectively rupturing the set of connections in the MIM capacitor may reduce the capacitance value of the MIM capacitor to a value approximately that of the target capacitance value.

公开(公告)号：US20210257989A1

公开(公告)日：2021-08-19

申请号：US17245901

申请日：2021-04-30

Applicant: QUALCOMM Incorporated

Inventor： Kai LIU ,  Rui TANG ,  Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Jonghae KIM

IPC: H03H9/54 ,  H01P1/203 ,  H03H3/02 ,  H03H9/05

Abstract: Aspects of the disclosure are directed to a bandpass filter including a first, second, third and fourth resonators, wherein the second and third resonators are in parallel, wherein the first resonator includes a first and second terminals, wherein the second resonator includes a second resonator top terminal and a second resonator bottom terminal, wherein the third resonator includes a third resonator top terminal and a third resonator bottom terminal, wherein the fourth resonator includes a third terminal and a fourth terminal; wherein the first terminal is coupled to the second resonator top terminal, wherein the second terminal is coupled to the third resonator top terminal, wherein the third terminal is coupled to the third resonator bottom terminal, wherein the fourth terminal is coupled to the second resonator bottom terminal; a first inductor coupled to the first and third terminals; and a second inductor coupled to the second and fourth terminals.