公开(公告)号：US11694993B2

公开(公告)日：2023-07-04

申请号：US17499134

申请日：2021-10-12

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Weihua Cheng ,  Jun Liu

IPC: H01L25/18 ,  H01L25/065 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/78 ,  H01L24/08 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes NAND memory cells and a first bonding layer including first bonding contacts. The semiconductor device also includes a second semiconductor structure including DRAM cells and a second bonding layer including second bonding contacts. The semiconductor device also includes a third semiconductor structure including a processor, SRAM cells, and a third bonding layer including third bonding contacts. The semiconductor device further includes a first bonding interface between the first and third bonding layers, and a second bonding interface between the second and third bonding layers. The first bonding contacts are in contact with a first set of the third bonding contacts at the first bonding interface. The second bonding contacts are in contact with a second set of the third bonding contacts at the second bonding interface. The first and second bonding interfaces are in a same plane.

公开(公告)号：US20230118453A1

公开(公告)日：2023-04-20

申请号：US18083198

申请日：2022-12-16

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu ,  Weihua Cheng

IPC: H01L25/065 ,  H01L21/78 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, first semiconductor structures are formed. At least one of the first semiconductor structures includes a processor, static random-access memory (SRAM) cells, and a first bonding layer comprising first bonding contacts. Second semiconductor structures are formed. At least one of the second semiconductor structures comprises dynamic random-access memory (DRAM) cells and a second bonding layer comprising second bonding contacts. The first semiconductor structures and the second semiconductor structures are bonded. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure. At least one of the first semiconductor structures and the second semiconductor structures further includes a peripheral circuit.

公开(公告)号：US11600637B2

公开(公告)日：2023-03-07

申请号：US17116231

申请日：2020-12-09

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Jun Liu ,  Zongliang Huo

IPC: H01L27/11582 ,  H01L21/02 ,  H01L21/225 ,  H01L21/306 ,  H01L21/311 ,  H01L27/1157 ,  H01L29/10 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/321

Abstract: Embodiments of three-dimensional memory device architectures and fabrication methods therefore are disclosed. In an example, the memory device includes a substrate having a first layer stack on it. The first layer stack includes alternating conductor and insulator layers. A second layer stack is disposed over the first layer stack where the second layer stack also includes alternating conductor and insulator layers. One or more vertical structures extend through the first layers stack. A conductive material is disposed on a top surface of the one or more vertical structures. One or more second vertical structures extend through the second layer stack and through a portion of the conductive material.

公开(公告)号：US11562985B2

公开(公告)日：2023-01-24

申请号：US17157776

申请日：2021-01-25

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu ,  Weihua Cheng

IPC: H01L27/11 ,  H01L25/065 ,  H01L21/78 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a processor, an array of SRAM cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of DRAM cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer in are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one of the dies includes the bonded first and second semiconductor structures.

公开(公告)号：US11552056B2

公开(公告)日：2023-01-10

申请号：US17459339

申请日：2021-08-27

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu

IPC: G11C11/34 ,  H01L25/065 ,  G11C13/00 ,  G11C16/04 ,  G11C16/10 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: Three-dimensional (3D) memory devices with 3D phase-change memory (PCM) and methods for forming and operating the 3D memory devices are disclosed. In an example, a 3D memory device includes a first semiconductor structure including an array of NAND memory cells, and a first bonding layer including first bonding contacts. The 3D memory device also further includes a second semiconductor structure including a second bonding layer including second bonding contacts, a semiconductor layer and a peripheral circuit and an array of PCM cells between the second bonding layer and the semiconductor layer. The 3D memory device further includes a bonding interface between the first and second bonding layers. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

公开(公告)号：US11430766B2

公开(公告)日：2022-08-30

申请号：US16669435

申请日：2019-10-30

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu ,  Weihua Cheng

IPC: H01L27/24 ,  H01L25/065 ,  H01L21/78 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a processor, an array of static random-access memory (SRAM) cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of dynamic random-access memory (DRAM) cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

公开(公告)号：US20220093614A1

公开(公告)日：2022-03-24

申请号：US17540224

申请日：2021-12-01

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu ,  Weihua Cheng

IPC: H01L27/1157 ,  H01L21/50 ,  H01L23/00 ,  H01L27/06 ,  H01L27/108 ,  H01L27/11578

Abstract: Embodiments of bonded unified semiconductor chips and fabrication and operation methods thereof are disclosed. In an example, a method for forming a unified semiconductor chip is disclosed. A first semiconductor structure is formed. The first semiconductor structure includes one or more processors, an array of embedded DRAM cells, and a first bonding layer including a plurality of first bonding contacts. A second semiconductor structure is formed. The second semiconductor structure includes an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the first bonding contacts are in contact with the second bonding contacts at a bonding interface.

公开(公告)号：US20220059482A1

公开(公告)日：2022-02-24

申请号：US17521332

申请日：2021-11-08

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first bonding layer having a plurality of first bonding contacts, and a first via structure extending vertically through the first bonding layer and into the first semiconductor structure. The second semiconductor structure includes a second bonding layer having a plurality of second bonding contacts, and a second via structure extending vertically through the second bonding layer and into the second semiconductor structure. The first bonding contacts are in contact with the second bonding contacts at the bonding interface, the first via structure is in contact with the second via structure, and sidewalls of the first via structure and the second via structures have a staggered profile at the bonding interface.

公开(公告)号：US20210151413A1

公开(公告)日：2021-05-20

申请号：US17141022

申请日：2021-01-04

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu

IPC: H01L25/065 ,  G11C13/00 ,  G11C16/04 ,  G11C16/10 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: Three-dimensional (3D) memory devices with 3D phase-change memory (PCM) and methods for forming and operating the 3D memory devices are disclosed. In an example, a 3D memory device includes a first semiconductor structure including a substrate, an array of NAND memory cells above the substrate, and a first bonding layer above the array of NAND memory cells. The first bonding layer includes first bonding contacts. The 3D memory device also further includes a second semiconductor structure including a second bonding layer above the first bonding layer and including second bonding contacts, a peripheral circuit and an array of PCM cells above the second bonding layer, and a semiconductor layer above and in contact with the peripheral circuit. The 3D memory device further includes a bonding interface between the first and second bonding layers. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

公开(公告)号：US20210111342A1

公开(公告)日：2021-04-15

申请号：US16727853

申请日：2019-12-26

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu

IPC: H01L45/00 ,  G11C13/00

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A lower bit line contact and a lower bit line in contact with the lower bit line contact are formed. Lower memory cells are formed above and in contact with the lower bit line. Each lower memory cell includes stacked a phase-change memory (PCM) element, a selector, and electrodes. Parallel word lines in a same plane are formed above and in contact with the lower memory cells. Each word line is perpendicular to the lower bit line. Upper memory cells are formed above and in contact with the word lines. Each upper memory cell includes stacked a PCM element, a selector, and electrodes. An upper bit line is formed above and in contact with the upper memory cells. The upper bit line is perpendicular to each word line. An upper bit line contact is formed above and in contact with the upper bit line. At least one of the lower bit line contact and the upper bit line contact is disposed inclusively between the lower and upper memory cells in a plan view.