公开(公告)号：US06882753B2

公开(公告)日：2005-04-19

申请号：US09874559

申请日：2001-06-04

Applicant: Cheng-Hsien Chen ,  Chen-Yi Lee ,  Lin-Tien Mei ,  Hung-Ta Pai

Inventor： Cheng-Hsien Chen ,  Chen-Yi Lee ,  Lin-Tien Mei ,  Hung-Ta Pai

IPC: G06T9/00 ,  H04N7/26 ,  H04N7/30 ,  G06K9/46

CPC classification number: G06T9/007 ,  H04N19/124 ,  H04N19/152 ,  H04N19/17 ,  H04N19/192 ,  H04N19/48 ,  H04N19/60

Abstract: A method is adapted for compressing an image data block, and includes the steps of: (a) subjecting the image data block to discrete cosine transformation so as to generate discrete cosine transform data; (b) quantizing the discrete cosine transform data in accordance with a quantizer matrix that consists of an array of quantizing coefficients so as to generate quantized data; (c) encoding the quantized data using an entropy coding algorithm so as to generate an encoded bitstream; and (d) when the length of the encoded bitstream does not fall within a predetermined range, adjusting the quantizing coefficients in the quantizer matrix and repeating steps (b) and (c) until the length of the encoded bitstream falls within the predetermined range.

Abstract translation: 一种适于压缩图像数据块的方法，包括以下步骤：（a）对图像数据块进行离散余弦变换，以产生离散余弦变换数据; （b）根据由量化系数阵列组成的量化器矩阵量化离散余弦变换数据，以产生量化数据; （c）使用熵编码算法对所述量化数据进行编码，以便生成编码比特流; 和（d）当编码比特流的长度不落在预定范围内时，调整量化器矩阵中的量化系数并重复步骤（b）和（c），直到编码比特流的长度落在预定范围内。

公开(公告)号：US06882037B2

公开(公告)日：2005-04-19

申请号：US10213077

申请日：2002-08-07

Applicant: Wei-Feng Lin ,  Wei-Chi Liu ,  Chung-Ju Wu

Inventor： Wei-Feng Lin ,  Wei-Chi Liu ,  Chung-Ju Wu

IPC: H01L21/58 ,  H01L23/498 ,  H01L23/48

CPC classification number: H01L24/83 ,  H01L23/49838 ,  H01L24/29 ,  H01L2224/2919 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/00

Abstract: A die paddle for receiving an integrated circuit die in a plastic substrate. The die paddle is defined by a copper film on the plastic substrate and comprises a plurality of via holes through the plastic substrate, a plurality of opening through the copper film, and a gold-containing ring formed on the peripheral portion of the copper film. The outermost openings (and/or the outermost via holes) and the gold-containing ring are separated by a distance of about 1 to about 20 mils.

Abstract translation: 一种用于在塑料基板中接收集成电路管芯的裸片。 模板由塑料基板上的铜膜限定，并且包括穿过塑料基板的多个通孔，穿过铜膜的多个开口以及形成在铜膜周边部分上的含金环。 最外面的开口（和/或最外通孔）和含金环分开约1至约20密耳的距离。

公开(公告)号：US20040119890A1

公开(公告)日：2004-06-24

申请号：US10323671

申请日：2002-12-20

Applicant: Silicon Integrated Systems Corp.

Inventor： Wen-Kuo Lin ,  Jong-Ho Yan

IPC: H04N005/08

CPC classification number: H04N7/012

Abstract: A method for detecting dynamic video pixels by using adaptive counter threshold values according to field difference value of the frame in the video, thereby to determine whether the frame is an interlaced frame or a progressive frame and to eliminate incorrect judgements resulting from field difference and to improve accuracy of frame determination.

Abstract translation: 一种通过使用根据视频中的帧的场差值的自适应计数器阈值来检测动态视频像素的方法，从而确定该帧是隔行扫描帧还是逐行帧，并且消除由场差引起的不正确判断，并且 提高帧确定的准确性。

公开(公告)号：US20040010625A1

公开(公告)日：2004-01-15

申请号：US10191213

申请日：2002-07-09

Applicant: Silicon Integrated Systems Corp.

Inventor： Lih-Shang Lo ,  Chuan Liu

IPC: G06F015/16

CPC classification number: H04L69/324

Abstract: An interface device for the synchronous transfer of data over serial ATA. The link layer portion receives the data from a device. The status monitor detects the status of the link layer portion. The fix pattern generator provides primitive formats responding to the status of the link layer portion. The physical layer controller directly returns the primitive formats to the device without sending or receiving the primitive formats to the link layer portion.

Abstract translation: 用于通过串行ATA同步传输数据的接口设备。 链路层部分从设备接收数据。 状态监视器检测链路层部分的状态。 固定模式生成器提供响应于链路层部分的状态的原始格式。 物理层控制器直接将原始格式返回到设备，而不向链路层部分发送或接收原始格式。

公开(公告)号：US20040010531A1

公开(公告)日：2004-01-15

申请号：US10191168

申请日：2002-07-09

Applicant: Silicon Integrated Systems Corp.

Inventor： Chung-Yen Lu ,  Kuo-Wei Yeh

IPC: G06F007/44

CPC classification number: G06F1/0356 ,  G06F7/483 ,  G06F7/556 ,  G06F2101/10

Abstract: An apparatus for calculating an exponential calculating result for a base 2 floating-point number comprises a transforming device, K exponential tables and a multiplier. The transforming device receives the floating-point number, transforms the floating-point number to an integer part and a fractional part and outputs the integer part and the fractional part. The fractional part is an N-bit number and divided into K parts which have N1, N2, . . . , NK bits respectively, wherein NnullN1nullN2null . . . nullNK. Each of the exponential tables receives one of the K parts divided from the fractional part and outputs a result. The multiplier receives all results from the exponential tables and outputs a mantissa. The integer part outputted form the transforming device is an exponent. The mantissa, the exponent and a sign whose value is 0 is used to represent an exponential calculating result which is represented in the following format: (null1)Synull2Eynullmy, where Sy is the sign whose value is 0, Ey is the integer part, my is the mantissa and lnullmy

Abstract translation: 用于计算基本2浮点数的指数计算结果的装置包括变换装置，K个指数表和乘数。 变换设备接收浮点数，将浮点数转换为整数部分和小数部分，并输出整数部分和小数部分。 小数部分是N位数，并分为具有N1，N2的K个部分。 。 。 ，NK位，其中N = N1 + N2 +。 。 。 + NK。 每个指数表接收从小数部分中分离的K个部分中的一个，并输出结果。 乘数从指数表接收所有结果并输出尾数。 从变换装置输出的整数部分是指数。 尾数，指数和值为0的符号用于表示以下格式表示的指数计算结果：（-1） .2 .my，其中Sy是其值的符号 是0，Ey是整数部分，我是尾数，l <= My <2。

公开(公告)号：US20030146478A1

公开(公告)日：2003-08-07

申请号：US10382842

申请日：2003-03-07

Applicant: SILICON INTEGRATED SYSTEMS CORP.

Inventor： Wen Ping Yen ,  Yun Hsiu Chen ,  Hung-Cheng Weng

IPC: H01L029/76 ,  H01L031/062 ,  H01L021/8234

CPC classification number: H01L29/51 ,  H01L21/28114 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/823462 ,  H01L29/42376 ,  H01L29/511 ,  H01L29/513

Abstract: A MOS device with dual gate insulators has a first gate insulator formed on a predetermined area of a semiconductor substrate, and a second gate insulator formed outside the predetermined area of the semiconductor substrate to surround the first gate insulator. The second gate insulator is thicker than the first gate insulator. In addition, a gate electrode layer is patterned on the dual gate insulators. The bottom center of the gate electrode layer covers the first gate insulator, and the bottom edge of the gate electrode layer extends to cover the second gate insulator.

公开(公告)号：US20030043161A1

公开(公告)日：2003-03-06

申请号：US09947803

申请日：2001-09-06

Applicant: SILICON INTEGRATED SYSTEMS CORP.

Inventor： Jaw-Chih Tseng ,  Chung-Chieh Liu

IPC: G09G005/00

CPC classification number: G09G5/001 ,  G09G5/363

Abstract: The present invention discloses an apparatus and method for bitmapping and synchronization. The present invention increases the serial number of a graphic command issued by a CPU. A page number of a display memory bitmapping to a graphic commands and a serial number of the graphic command are stored in a system memory connected to a CPU. The CPU directly accesses the display memory until the serial number corresponding to the page number stored in the page info equal to the page number of the graphic command issued currently by the CPU is less than the serial number of the graphic command executed currently by the graphic accelerator and the problem of data inconsistency could be neglected.

Abstract translation: 本发明公开了一种用于位图和同步的装置和方法。 本发明增加了由CPU发出的图形命令的序列号。 对图形命令和图形命令的序列号进行位图的显示存储器的页码存储在连接到CPU的系统存储器中。 CPU直接访问显示存储器，直到与页面信息中存储的页码相对应的序列号等于CPU当前发布的图形命令的页码小于图形当前执行的图形命令的序列号 加速器和数据不一致的问题可以忽略不计。

公开(公告)号：US5731809A

公开(公告)日：1998-03-24

申请号：US499939

申请日：1995-07-10

Applicant: Hung-Ming Lin ,  Mao-Yuan Ku

Inventor： Hung-Ming Lin ,  Mao-Yuan Ku

IPC: G09G5/39 ,  G09G5/00

CPC classification number: G09G5/39 ,  G09G2360/12

Abstract: An adaptive display memory management system for using idled display memory in a video graphics adapter card as extra system memory of a personal computer is presented. By means of hardware implementation, the memory management system manages the video display memory according to the video display mode and takes advantage of the idled display memory in forming virtual system memory for the computer, so that the working space of executing a user program is increased and the system performance of the computer is enhanced.

Abstract translation: 本发明提供了一种用于在视频图形适配器卡中使用空闲显示存储器作为个人计算机的额外系统存储器的自适应显示存储器管理系统。 通过硬件实现，存储器管理系统根据视频显示模式管理视频显示存储器，并利用空闲的显示存储器形成用于计算机的虚拟系统存储器，从而增加执行用户程序的工作空间 并且提高了计算机的系统性能。

公开(公告)号：US5682522A

公开(公告)日：1997-10-28

申请号：US503704

申请日：1995-07-18

Applicant: Hung-Ju Huang ,  Hung-Ming Lin

Inventor： Hung-Ju Huang ,  Hung-Ming Lin

IPC: G06F3/14 ,  G06F12/08 ,  G06F15/167 ,  G09G1/16 ,  G09G5/00 ,  G09G5/36 ,  G09G5/39

CPC classification number: G09G5/001 ,  G06F12/0866 ,  G06F15/167 ,  G06F3/14 ,  G09G5/363 ,  G09G5/39 ,  G06F2212/311 ,  G09G2360/121

Abstract: A shared memory architecture of graphics frame buffer and hard disk cache is presented. The architecture includes a system bus interface, a hard disk controller, a graphics controller, an arbiter, a memory and a shared memory block. The shared memory block is divided into graphics frame buffer memory and hard disk controller cache memory. The arbiter determines the shared memory access priority between the graphics controller and the hard disk controller. By mean of hardware implementation, memories can be shared by the graphics controller and the disk controller. The complexity of the system is reduced and the system performance is enhanced. The overall system cost is decreased.

Abstract translation: 提出了图形帧缓冲器和硬盘缓存的共享存储器架构。 该架构包括系统总线接口，硬盘控制器，图形控制器，仲裁器，存储器和共享存储器块。 共享内存块分为图形缓冲存储器和硬盘控制器缓存。 仲裁器确定图形控制器和硬盘控制器之间的共享内存访问优先级。 通过硬件实现，存储器可以由图形控制器和磁盘控制器共享。 降低系统的复杂性，提高系统性能。 整体系统成本下降。

公开(公告)号：US20240388113A1

公开(公告)日：2024-11-21

申请号：US18664966

申请日：2024-05-15

Applicant: SILICON INTEGRATED SYSTEMS CORP.

Inventor： Song Sheng LIN ,  Keng-Nan CHEN

IPC: H02J7/00

Abstract: A constant current charging device is configured to charge a device to be charged and includes: a reference current source configured to provide a reference current; a current mirror electrically coupled to the reference current source and configured to output a mirror current; a current adjustment control unit electrically coupled to the current mirror and the device to be charged wherein the current adjustment control unit is configured to output a charging current according to the mirror current to charge the device to be charged; and a current compensation unit electrically coupled to the current mirror and the current adjustment control unit. The current adjustment control unit includes a voltage follower unit, and the current adjustment control unit tracks a charging voltage through the voltage follower unit to stabilize the charging current.