公开(公告)号：US20160372165A1

公开(公告)日：2016-12-22

申请号：US15251770

申请日：2016-08-30

Applicant: Micron Technology, Inc.

Inventor： Timothy B. Cowles ,  Steven M. Bodily

IPC: G11C7/06 ,  G11C8/10 ,  G11C7/22 ,  G11C7/10

CPC classification number: G11C7/065 ,  G11C5/06 ,  G11C7/06 ,  G11C7/08 ,  G11C7/1006 ,  G11C7/1036 ,  G11C7/22 ,  G11C8/10 ,  G11C11/4091 ,  G11C19/00 ,  G11C2207/002 ,  G11C2207/005

Abstract: The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense line of an array, a first isolation device located between the first memory cell and first sensing circuitry corresponding thereto, and a second isolation device located between the first memory cell and second sensing circuitry corresponding to a second sense line. The first and the second isolation devices are operated to shift data in the array without transferring the data via an input/output line of the array.

公开(公告)号：US09477626B2

公开(公告)日：2016-10-25

申请号：US14148031

申请日：2014-01-06

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G06F3/00 ,  G06F13/40 ,  G01R31/3185 ,  G06F3/06 ,  G06F13/38 ,  H04L29/08

CPC classification number: G11C7/1036 ,  G01R31/318572 ,  G06F3/0601 ,  G06F13/385 ,  G06F13/40 ,  G06F13/4022 ,  G06F13/4291 ,  G11C7/1066 ,  H04L29/08549

Abstract: A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One pin carries data bi-directionally and address and instruction information from a controller to a selected port. The other pin carries a clock signal from the controller to a target port or ports in or on the desired circuit or circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is minimal. The bus is used for communication, such as serial communication related to the functional operation of an IC or core design, or serial communication related to test, emulation, debug, and/or trace operations of an IC or core design.

Abstract translation: 双引脚通信接口总线和控制电路与集成电路中的电路板，集成电路或嵌入式核心一起使用。 一个引脚将数据双向传输，并将地址和指令信息从控制器传送到所选端口。 另一个引脚将时钟信号从控制器传送到所需电路或电路中或其上的目标端口或端口。 总线可用于串行访问电路，其中IC上的引脚或芯上的端子的可用性最小。 总线用于通信，例如与IC或核心设计的功能操作有关的串行通信，或与IC或核心设计的测试，仿真，调试和/或跟踪操作相关的串行通信。

公开(公告)号：US09437256B2

公开(公告)日：2016-09-06

申请号：US14660219

申请日：2015-03-17

Applicant: Micron Technology, Inc.

Inventor： Timothy B. Cowles ,  Steven M. Bodily

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/08 ,  G11C11/4091 ,  G11C19/00 ,  G11C5/06

CPC classification number: G11C7/065 ,  G11C5/06 ,  G11C7/06 ,  G11C7/08 ,  G11C7/1006 ,  G11C7/1036 ,  G11C7/22 ,  G11C8/10 ,  G11C11/4091 ,  G11C19/00 ,  G11C2207/002 ,  G11C2207/005

Abstract: The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense line of an array, a first isolation device located between the first memory cell and first sensing circuitry corresponding thereto, and a second isolation device located between the first memory cell and second sensing circuitry corresponding to a second sense line. The first and the second isolation devices are operated to shift data in the array without transferring the data via an input/output line of the array.

Abstract translation: 本公开包括与数据移位相关的装置和方法。 示例性设备包括耦合到阵列的第一感测线的第一存储器单元，位于第一存储器单元和与其对应的第一感测电路之间的第一隔离器件，以及位于第一存储器单元和第二感测电路之间的第二隔离器件 对应于第二感测线。 操作第一和第二隔离装置以移动阵列中的数据，而不经由阵列的输入/输出线传送数据。

公开(公告)号：US09424034B2

公开(公告)日：2016-08-23

申请号：US13931008

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Glenn Hinton ,  Bret Toll ,  Ronak Singhal

IPC: G06F9/04 ,  G06F9/30

CPC classification number: G11C7/1036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30163

Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.

Abstract translation: 处理器包括N位寄存器和用于接收多寄存器存储器访问指令的解码单元。 多寄存器存储器访问指令是指示存储器位置和寄存器。 处理器包括与解码单元和N位寄存器耦合的存储器存取单元。 存储器访问单元响应于多个寄存器存储器访问指令执行多个寄存器存储器存取操作。 该操作涉及在包括指定的寄存器的每个N位寄存器中涉及N位数据。 该操作还涉及对应于所指示的存储器位置的M×N位存储器线的不同对应的N位部分。 要在多个寄存器存储器访问操作中涉及的N位寄存器中的N位数据的总位数至少等于存储器行的M×N位的至少一半。

公开(公告)号：US20160141009A1

公开(公告)日：2016-05-19

申请号：US14636814

申请日：2015-03-03

Applicant: SK hynix Inc.

Inventor： Ho Sung CHO

IPC: G11C7/10 ,  G11C16/32 ,  G06F9/30

CPC classification number: G11C7/1036 ,  G06F9/30105 ,  G06F9/30134 ,  G11C16/10 ,  G11C16/32 ,  G11C29/1201 ,  H03M9/00

Abstract: A semiconductor apparatus including a register input selection block configured to serially receive input data and output the input data in parallel as first and second data sets, or receive register selection output signals and output the register selection output signals as the first and second data sets, in response to a shift control signal and a capture control signal; a first data register configured to receive and store the first data set and output stored data as first register output signals; a second data register configured to receive and store the first and second data sets and output stored data as second register output signals; a register output selection block configured to output ones of the first and second register output signals as the register selection output signals; and a data output selection block configured to serially output one of the first and second data sets as output data.

Abstract translation: 一种半导体装置，包括寄存器输入选择块，被配置为串行地接收输入数据并且并行地输出输入数据作为第一和第二数据组，或者接收寄存器选择输出信号，并且将寄存器选择输出信号作为第一和第二数据集输出， 响应于移位控制信号和捕获控制信号; 第一数据寄存器，被配置为接收和存储第一数据组，并将存储的数据作为第一寄存器输出信号输出; 第二数据寄存器，被配置为接收和存储第一和第二数据组并输出存储的数据作为第二寄存器输出信号; 寄存器输出选择块，被配置为输出第一和第二寄存器输出信号中的一个作为寄存器选择输出信号; 以及数据输出选择块，被配置为串行地输出第一和第二数据集之一作为输出数据。

公开(公告)号：US09153295B2

公开(公告)日：2015-10-06

申请号：US14045995

申请日：2013-10-04

Applicant: Texas Instruments Incorporated

Inventor： Pratheesh Gangadhar Thalakkal Kottilaveedu ,  William C Wallace

IPC: G06F13/12 ,  G06F13/00 ,  G11C7/10 ,  G11C8/04 ,  G06F9/30

CPC classification number: G11C7/1036 ,  G06F9/3012 ,  G11C8/04

Abstract: Scratch pad register banks are used as shared fast access storage between processors in a multi processor system. Instead of the usual one to one register mapping between the processors and the scratch pad register banks, an any to any mapping is implemented. The utilization of the scratch pad register banks is improved as the any to any mapping of the registers allow the storage of any processor register anywhere in the scratch pad register bank.

Abstract translation: 划痕寄存器组用作多处理器系统中的处理器之间的共享快速存取存储。 代替处理器和暂存寄存器组之间通常的一对一寄存器映射，实现任何到任何映射。 缓冲寄存器组的使用得到改善，因为对寄存器的任何映射允许将任何处理器寄存器存储在暂存器寄存器组中的任何地方。

公开(公告)号：US09076506B2

公开(公告)日：2015-07-07

申请号：US13630163

申请日：2012-09-28

Applicant: Wanfang Tsai

Inventor： Wanfang Tsai

IPC: G11C7/00 ,  G11C7/10 ,  G11C19/00 ,  G11C16/08 ,  G11C29/00

CPC classification number: G11C7/1036 ,  G11C16/08 ,  G11C19/00 ,  G11C29/82 ,  G11C2207/107 ,  G11C2211/5642

Abstract: A shift register structure is presented that can be used in variable rate parallel to serial data conversions. In an N to 1 conversion, data is received from an (N×m)-wide parallel data bus in an N by m wide latch. This data can include m-bit wide units of data are to be ignore and the parallel bus clock will be of variable rate due to this data to be skipped, which is not to be put out on to the serial bus. The data is transferred from the latch to an N unit shift register, each unit holding m-bits. Multiplexing circuitry is included so that at least on unit of the shift can receive data from more than one latch location, thereby reducing the number of units in the shift register that may need to be skipped when the data is transferred out on to an m-bit wide serial bus with the bits to be ignored absent.

Abstract translation: 提出了可以以可变速率并行到串行数据转换的方式使用移位寄存器结构。 在N到1转换中，以N×m宽的锁存器从（N×m）范围的并行数据总线接收数据。 该数据可以包括要忽略的m位宽的数据单元，并且由于要跳过的数据，并行总线时钟将是可变速率的，这不会被输出到串行总线。 数据从锁存器传送到N单元移位寄存器，每个单元保持m位。 包括多路复用电路，使得至少在移位单元上可以从多于一个锁存位置接收数据，从而减少当数据被传送到m位时可能需要跳过的移位寄存器中的单元数， 位宽的串行总线与被忽略的位不存在。

公开(公告)号：US08949493B1

公开(公告)日：2015-02-03

申请号：US12847761

申请日：2010-07-30

Applicant: Curt Wortman ,  Chong H. Lee ,  Huy Ngo

Inventor： Curt Wortman ,  Chong H. Lee ,  Huy Ngo

IPC: G06F3/00 ,  G06F13/00 ,  G06F5/00 ,  G06F13/12 ,  G06M3/00 ,  G11C19/00 ,  G01R31/28 ,  G06F17/50 ,  G06F1/02 ,  G06F7/58 ,  H04L9/00

CPC classification number: H04L25/03866 ,  G06F3/00 ,  G06F5/00 ,  G06F7/58 ,  G06F13/00 ,  G06F13/12 ,  G06F13/40 ,  G06F13/4221 ,  G06F13/4282 ,  G11C7/1012 ,  G11C7/1036 ,  G11C19/00 ,  G11C19/285 ,  H04L9/00

Abstract: Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.

Abstract translation: 公开了与可配置加扰电路相关的各种结构和方法。 实施例可以被配置为支持多个协议中的一个。 一些实施例涉及可配置的多径扰频器，其可以适于组合跨越多个车道的加扰电路或者提供独立的基于车道的加扰器。 一些实施例可配置为选择加扰器类型。 一些实施例可配置为适应多个协议特定的加扰多项式之一。 一些实施例涉及在数据的最低有效位（“LSB”）和最高有效位（“MSB”）排序之间进行选择。 在一些实施例中，每个通道中的加扰器电路适于处理超过一位宽的数据。

公开(公告)号：US20150016193A1

公开(公告)日：2015-01-15

申请号：US14326199

申请日：2014-07-08

Applicant: Matthew LEWIS ,  Paulius DUPLYS

Inventor： Matthew LEWIS ,  Paulius DUPLYS

IPC: G11C7/10

CPC classification number: G11C7/1036 ,  G06F21/79 ,  G06F2221/2141

Abstract: A circuit configuration is described including a first input for inputting a first set of digital input data, an output for outputting digital output data, and a control input for receiving a control signal. At least two register units are provided and the circuit configuration is designed to write, as a function of the control signal, into a first register unit optionally at least a part of the first set of input data or of the second set of digital input data and to write into a second register unit optionally at least a part of the first set of input data or of the second set of input data.

Abstract translation: 描述了一种电路配置，其包括用于输入第一组数字输入数据的第一输入，用于输出数字输出数据的输出和用于接收控制信号的控制输入。 提供至少两个寄存器单元，并且电路配置被设计为根据控制信号将可写入的第一组输入数据或第二组数字输入数据集的至少一部分写入第一寄存器单元 并且可选择地将第一组输入数据或第二组输入数据的至少一部分写入第二寄存器单元。

公开(公告)号：US20140092690A1

公开(公告)日：2014-04-03

申请号：US13630163

申请日：2012-09-28

Applicant: Wanfang Tsai

Inventor： Wanfang Tsai

IPC: G11C7/10

CPC classification number: G11C7/1036 ,  G11C16/08 ,  G11C19/00 ,  G11C29/82 ,  G11C2207/107 ,  G11C2211/5642

Abstract: A shift register structure is presented that can be used in variable rate parallel to serial data conversions. In an N to I conversion, data is received from an (N×m)-wide parallel data bus in an N by in wide latch. This data can include m-bit wide units of data are to be ignore and the parallel bus clock will be of variable rate due to this data to be skipped, which is not to be put out on to the serial bus. The data is transferred from the latch to an N unit shift register, each unit holding m-bits. Multiplexing circuitry is included so that at least on unit of the shift can receive data from more than one latch location, thereby reducing the number of units in the shift register that may need to be skipped when the data is transferred out on to an m-bit wide serial bus with the bits to be ignored absent.

Abstract translation: 提出了可以以可变速率并行到串行数据转换的方式使用移位寄存器结构。 在N到I转换中，在宽锁存器中，N（N×m）范围内的并行数据总线接收数据。 该数据可以包括要忽略的m位宽的数据单元，并且由于要跳过的数据，并行总线时钟将是可变速率的，这不会被输出到串行总线。 数据从锁存器传送到N单元移位寄存器，每个单元保持m位。 包括多路复用电路，使得至少在移位单元上可以从多于一个锁存位置接收数据，从而减少当数据被传送到m位时可能需要跳过的移位寄存器中的单元数， 位宽的串行总线与被忽略的位不存在。