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    Chip structure to improve resistance-capacitance delay and reduce energy loss of the chip
    92.
    发明授权
    Chip structure to improve resistance-capacitance delay and reduce energy loss of the chip 有权
    芯片结构提高电阻电容延迟并减少芯片的能量损耗

    公开(公告)号：US06700162B2

    公开(公告)日：2004-03-02

    申请号：US10337673

    申请日：2003-01-06

    Applicant: Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ching-Cheng Huang

    Inventor： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ching-Cheng Huang

    IPC: H01L2348

    CPC classification number: H01L21/768 ,  H01L21/76807 ,  H01L21/76838 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/60 ,  H01L24/05 ,  H01L24/13 ,  H01L24/45 ,  H01L27/0676 ,  H01L27/08 ,  H01L28/10 ,  H01L28/20 ,  H01L2221/1036 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2224/45 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15174 ,  H01L2924/19041 ,  H01L2924/19051 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2224/48 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

    Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

    Abstract translation: 芯片结构包括基板，第一堆叠层，钝化层和第二堆积层。 基板包括放置在基板的表面上的许多电气装置。 第一组合层位于基底上。 第一组合层设置有第一电介质体和第一互连方案，其中第一互连方案与第一介电体内部交错并电连接到电气装置。 第一互连方案由第一金属层和插塞构成，其中相邻的第一金属层通过插塞电连接。 钝化层设置在第一堆叠层上并且设有暴露第一互连方案的开口。 第二堆叠层形成在钝化层上。 第二组合层设置有第二电介质体和第二互连方案，其中第二互连方案在第二介电体内部交织并与第一互连方案电连接。 第二互连方案由至少一个第二金属层和至少一个通孔金属填料构成，其中第二金属层电连接到通孔金属填料。 第二金属层的迹线的厚度，宽度和横截面积分别大于第一金属层的厚度，宽度和横截面面积。

    Method for forming wiring structure
    93.
    发明申请
    Method for forming wiring structure 失效
    形成布线结构的方法

    公开(公告)号：US20030224592A1

    公开(公告)日：2003-12-04

    申请号：US10448095

    申请日：2003-05-30

    Applicant: Matsushita Electric Industrial Co., Ltd.

    Inventor： Takeshi Harada

    IPC: H01L021/4763 ,  H01L021/44

    CPC classification number: H01L21/76807 ,  H01L21/3212 ,  H01L21/76882 ,  H01L21/76886 ,  H01L2221/1036

    Abstract: A recess is formed in an insulating film, and then a conductive film is deposited over the insulating film so as to fill the recess. Thereafter, the conductive film is subjected to a first heat treatment. Subsequently, part of the conductive film located outside the recess is removed, and then the remaining part of the conductive film is subjected to a second heat treatment with the surface thereof exposed.

    Abstract translation: 在绝缘膜中形成凹部，然后在绝缘膜上沉积导电膜以填充凹部。 然后，对导电膜进行第一次热处理。 接着，除去位于凹部外部的导电膜的一部分，然后对导电膜的剩余部分进行第二次热处理，其表面露出。

    Graded dielectric layer and method for fabrication thereof
    94.
    发明授权
    Graded dielectric layer and method for fabrication thereof 有权
    梯度介电层及其制造方法

    公开(公告)号：US06657284B1

    公开(公告)日：2003-12-02

    申请号：US09727634

    申请日：2000-12-01

    Applicant: Lain-Jong Li ,  Shwang-Ming Jeng ,  Syun-Ming Jang ,  Chen-Hua Yu

    Inventor： Lain-Jong Li ,  Shwang-Ming Jeng ,  Syun-Ming Jang ,  Chen-Hua Yu

    IPC: H01L2358

    CPC classification number: H01L21/76822 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76813 ,  H01L23/5329 ,  H01L2221/1031 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Within a method for forming a dielectric layer, there is first provided a substrate. There is then formed over the substrate a dielectric layer, wherein the dielectric layer is formed from a dielectric material comprising silicon, carbon and nitrogen. Preferably, a nitrogen content is graded within a thickness of the dielectric layer to provide an upper lying nitrogen rich contiguous surface layer of the dielectric layer and a lower lying nitrogen poor contiguous layer of the dielectric layer. The method contemplates a microelectronic fabrication having formed therein a dielectric layer formed in accord with the method. The method provides the resulting dielectric layer with a lower dielectric constant and enhanced adhesion properties as a substrate layer.

    Abstract translation: 在形成电介质层的方法中，首先提供衬底。 然后在衬底上形成介电层，其中介电层由包含硅，碳和氮的电介质材料形成。 优选地，氮含量在介电层的厚度内分级，以提供电介质层的上位氮富连续表面层和电介质层的较低位置的氮不良连续层。 该方法考虑了在其中形成有根据该方法形成的电介质层的微电子制造。 该方法提供了所得到的介电层具有较低介电常数和增强的作为基底层的粘合性能。

    Method of manufacturing semiconductor device
    95.
    发明授权
    Method of manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US06632738B2

    公开(公告)日：2003-10-14

    申请号：US09876207

    申请日：2001-06-06

    Applicant: Shuji Sone

    Inventor： Shuji Sone

    IPC: H01L2144

    CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76859 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An interlayer insulating film and a first via connected to a diffusion layer in a MOS transistor are formed on the diffusion layer. Then, a low dielectric constant film for a first layer copper interconnection, and the first layer copper interconnection connected to the first via are formed. Then, an etching stopper film, an interlayer insulating film, and a low dielectric constant film for a second layer copper interconnection are formed in this order. Then, a via hole is formed in the etching stopper film and the interlayer insulating film, and a groove is formed in the low dielectric constant film for the second layer copper interconnection. A barrier metal layer is then formed. Thereafter, Ar ions are implanted. At the time, the implantation energy is 50 keV, and the dose is 1×1017 cm−2. A second via and the second layer copper interconnection are formed, and annealing is performed at a temperature of 400° C.

    Abstract translation: 在扩散层上形成层间绝缘膜和连接到MOS晶体管中的扩散层的第一通孔。 然后，形成用于第一层铜互连的低介电常数膜和连接到第一通孔的第一层铜互连。 然后，依次形成蚀刻停止膜，层间绝缘膜和用于第二层铜互连的低介电常数膜。 然后，在蚀刻停止膜和层间绝缘膜中形成通孔，并且在用于第二层铜互连的低介电常数膜中形成沟槽。 然后形成阻挡金属层。 此后，植入Ar离子。 此时，植入能量为50keV，剂量为1×10 17 HIL> < - 2 。 形成第二通孔和第二层铜互连，并在400℃的温度下进行退火。

    Use of a silicon carbide adhesion promoter layer to enhance the adhesion of silicon nitride to low-k fluorinated amorphous carbon
    96.
    发明授权
    Use of a silicon carbide adhesion promoter layer to enhance the adhesion of silicon nitride to low-k fluorinated amorphous carbon 失效

    公开(公告)号：US06630396B2

    公开(公告)日：2003-10-07

    申请号：US10229656

    申请日：2002-08-27

    Applicant: Hongning Yang ,  Tue Nguyen

    Inventor： Hongning Yang ,  Tue Nguyen

    IPC: H01L214763

    CPC classification number: H01L21/76832 ,  C23C16/325 ,  C23C16/345 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/3127 ,  H01L21/314 ,  H01L21/3146 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76807 ,  H01L2221/1036

    Abstract: A plasma enhanced chemical vapor deposition (PECVD) process is provided for depositing one or more dielectric material layers on a substrate for use in interconnect structures of integrated circuits. The method comprises the steps of depositing a fluorinated amorphous carbon (a-F:C) layer on a substrate by providing a fluorine containing gas, preferably octafluorocyclobutane, and a carbon containing gas, preferably methane, in ratio of approximately 5.6, so as to deposit a a-F:C layer having an internal compressive stress of approximately 28 MPa. After deposition the film is annealed at approximately 400° C. for approximately two hours. An adhesion promoter layer of relatively hydrogen-free hydrogeneated silicon carbide is then deposited on the a-F:C layer using silane (SiH4) and methane (CH4) as the deposition gases. The silicon carbide layer may be deposited at a rate of approximately 180 Å per minute and typically results in deposition of a silicon carbide layer having an internal compressive stress of approximately 400 MPa. The deposited silicon carbide layer has relatively few hydrogen bonds thereby yielding a compact structure which promotes adhesion of the a-F:C layer to a silicon nitride layer and to the a-F:C layer, and which reduces diffusion of fluorine through the silicon carbide layer. A silicon nitride layer is then deposited on the adhesion promoter layer, the deposition materials preferably comprising silane (SiH4) and nitrogen (N2) in a ratio of 30:100 at 400° C. The silicon nitride layer has relatively few hydrogen bonds thereby resulting in a layer having an internal compressive stress of approximately 240 MPa. This stacked layer structure has thermal stability and resists peeling and cracking up to 450° C., and the a-F:C dielectric layer has a dielectric constant (k) as low, or lower, than 2.5.

    Selective metal passivated copper interconnect with zero etch stops
    98.
    发明申请
    Selective metal passivated copper interconnect with zero etch stops 审中-公开
    选择性金属钝化铜互连，零蚀刻停止

    公开(公告)号：US20030148618A1

    公开(公告)日：2003-08-07

    申请号：US10071995

    申请日：2002-02-07

    Applicant: Applied Materials, Inc.

    Inventor： Suketu A. Parikh

    IPC: H01L021/311

    CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76897 ,  H01L2221/1036

    Abstract: In one aspect of the invention, a method for forming interconnects on a substrate is provided. A metal passivation layer is selectively formed on conductive elements of the substrate. Thereafter, one or more dielectric layers are deposited over the metal passivation layer. Interconnect lines and vias are then patterned and etched into the one or more dielectric layers. A conductive layer is subsequently deposited over the interconnect lines and vias. In another aspect of the invention, the selective deposition process may comprise electroless deposition of the metal passivation layer. Alternatively, the selective deposition process may comprise a selective chemical vapor deposition process. The metal passivation layer may also be formed by depositing a metal alloy of copper over the conductive element, depositing a copper layer over the metal alloy, and annealing the metal alloy. In another aspect still, a metal passivation layer is selectively deposited over the conductive element of the substrate. A first dielectric layer is then deposited over the metal passivation layer and the substrate. This is followed by depositing a second dielectric layer over the first dielectric layer. Preferably, the first dielectric layer has a dielectric constant higher than a second dielectric constant of the second dielectric layer. It is also preferred that the first and second dielectric layers have dissimilar etch characteristics. Interconnect lines and vias are then etched in the first and second dielectric layers using selective etch chemistry. The interconnect lines and vias are then filled with at least one conductive material.

    Abstract translation: 在本发明的一个方面，提供了一种用于在基板上形成互连的方法。 在衬底的导电元件上选择性地形成金属钝化层。 此后，在金属钝化层上沉积一个或多个电介质层。 然后将互连线和通孔图案化并蚀刻到一个或多个电介质层中。 导电层随后沉积在互连线和通孔上。 在本发明的另一方面，选择性沉积工艺可以包括金属钝化层的无电沉积。 或者，选择性沉积工艺可以包括选择性化学气相沉积工艺。 金属钝化层也可以通过在导电元件上沉积铜的金属合金，在金属合金上沉积铜层并退火金属合金而形成。 在另一方面，仍然，在衬底的导电元件上选择性地沉积金属钝化层。 然后在金属钝化层和衬底上沉积第一电介质层。 然后在第一介电层上沉积第二介电层。 优选地，第一电介质层的介电常数高于第二介电层的第二介电常数。 还优选的是，第一和第二电介质层具有不同的蚀刻特性。 然后使用选择性蚀刻化学法在第一和第二介电层中蚀刻互连线和通孔。 然后用至少一种导电材料填充互连线和通孔。

    Dual damascene structure with carbon containing SiO2 dielectric layers
    100.
    发明授权
    Dual damascene structure with carbon containing SiO2 dielectric layers 失效
    具有含SiO 2介电层的双镶嵌结构

    公开(公告)号：US06593659B2

    公开(公告)日：2003-07-15

    申请号：US09837683

    申请日：2001-04-18

    Applicant: Takashi Yokoyama

    Inventor： Takashi Yokoyama

    IPC: H01L2348

    CPC classification number: H01L21/76829 ,  H01L21/02126 ,  H01L21/02131 ,  H01L21/02134 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76834 ,  H01L2221/1036

    Abstract: A semiconductor device with dual damascene structure is provided, which suppresses propagation delay of signals without using complicated processes. The device comprises a semiconductor substrate having a lower wiring layer and electronic elements, a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer made of carbon-containing SiO2, a third dielectric layer on the second dielectric layer, a fourth dielectric layer on the third dielectric layer made of carbon containing SiO2, the first and second dielectric layers having a via hole, the third dielectric layer having a recess overlapping the via hole, the recess formed to communicate with the via hole, a metal plug formed in the via hole in contact with the lower wiring layer or the electronic elements in the substrate, a metal wiring layer formed in the recess, and a fourth dielectric layer to cover the metal wiring layer.

    Abstract translation: 提供了具有双镶嵌结构的半导体器件，其抑制信号的传播延迟而不使用复杂的工艺。 该器件包括具有下布线层和电子元件的半导体衬底，衬底上的第一介电层，由含碳SiO 2制成的第一电介质层上的第二电介质层，第二电介质层上的第三介电层， 所述第三电介质层由含有SiO 2的碳制成的第三电介质层，所述第一和第二电介质层具有通孔，所述第三电介质层具有与所述通孔重叠的凹部，所述凹部与所述通孔连通，金属插塞 形成在与下布线层或基板中的电子元件接触的通孔中，形成在凹部中的金属布线层和覆盖金属布线层的第四介电层。

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