公开(公告)号：US11776813B2

公开(公告)日：2023-10-03

申请号：US17511042

申请日：2021-10-26

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Cheng-Hsiang Fan

IPC: H01L21/033 ,  H01L21/308 ,  H01L21/762 ,  H01L21/768 ,  H01L21/764 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/308 ,  H01L21/31144 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76229 ,  H01L21/76816 ,  H01L21/76885 ,  H01L2221/1036

Abstract: The present disclosure provides a method for preparing a semiconductor device structure with fine patterns at different levels. The method includes forming a hard mask material over a substrate; etching the hardmask material to form hard mask pillars; forming spacers over sidewall surfaces of the hard mask pillars; etching the hard mask pillars and the target material by using the spacers as a mask to integrally forming a plurality of target structures, a high-level recesses in one of the plurality of target structures and a low-level recess between two target structures; and integrally forming a high-level conductive pattern in the high-level conductive pattern and a low-level conductive pattern in the low-level recess.

公开(公告)号：US20230307288A1

公开(公告)日：2023-09-28

申请号：US17701938

申请日：2022-03-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-CHEN PAN

IPC: H01L21/768 ,  H01L21/027

CPC classification number: H01L21/76807 ,  H01L21/76829 ,  H01L21/0274 ,  H01L2221/1036 ,  G03F1/38

Abstract: The present application discloses a method for fabricating a semiconductor device including: providing a photomask including an opaque layer on a mask substrate and surrounding a translucent layer on the mask substrate; forming a pre-process mask layer on a device stack; patterning the pre-process mask layer using the photomask to form a patterned mask layer including a mask region corresponding to the opaque layer, a trench region corresponding to the translucent layer, and a via hole corresponding to the mask opening of via feature; performing a damascene etching process to form a via opening and a trench opening in the device stack; and forming a via in the via opening and a trench in the trench opening. The translucent layer includes a mask opening of via feature which exposes a portion of the mask substrate. A thickness of the trench region is less than a thickness of the mask region.

公开(公告)号：US09960080B2

公开(公告)日：2018-05-01

申请号：US15199147

申请日：2016-06-30

Applicant: IMEC vzw

Inventor： Eric Beyne

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/4763 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L21/02 ,  H01L23/00

CPC classification number: H01L21/76898 ,  H01L21/02063 ,  H01L21/02118 ,  H01L21/0212 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76877 ,  H01L23/481 ,  H01L24/80 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/1036 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2225/06544 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

Abstract: A method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded by a direct bonding technique to form a wafer assembly, and the multiple IC devices are provided with metal contact structures. A TSV (Through Semiconductor Via) is produced through the bonded wafer assembly. The IC device or devices in the upper wafer or wafers have contact structures that serve as masks for the etching of the TSV opening. A conformal isolation liner is deposited in the TSV opening, and subsequently removed from the bottom and any horizontal areas in the TSV opening, while maintaining the liner on the sidewalls, followed by deposition of a TSV plug in the TSV opening. The removal of the liner is done without applying a lithography step.

公开(公告)号：US20180090369A1

公开(公告)日：2018-03-29

申请号：US15449712

申请日：2017-03-03

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Toshiyuki SASAKI

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76808 ,  H01L21/0268 ,  H01L21/027 ,  H01L21/0332 ,  H01L21/308 ,  H01L21/31144 ,  H01L21/76813 ,  H01L2221/1026 ,  H01L2221/1031 ,  H01L2221/1036

Abstract: A semiconductor device manufacturing method includes forming a first hole in a first processed layer. A first sacrificial film is formed in the first hole. A hole portion is formed in the first sacrificial film. A second sacrificial film is formed in the hole portion. A second processed layer is formed above the first sacrificial film and the second sacrificial film, and a second hole is formed in the second processed layer to expose the second sacrificial film. A third sacrificial film is formed on an inner side surface of the second hole, and a fourth sacrificial film is formed on the third sacrificial film. The second sacrificial film is etched using the fourth sacrificial film as a mask. The third sacrificial film exposed by etching the second sacrificial film is etched. The second processed layer is etched using the third sacrificial film as a mask.

公开(公告)号：US20180033684A1

公开(公告)日：2018-02-01

申请号：US15726590

申请日：2017-10-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sunil Kumar Singh ,  Chung-Ju Lee ,  Tien-I Bao

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1026 ,  H01L2221/1031 ,  H01L2221/1036 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments relate to a semiconductor device manufacturing process. In the process, a substrate is provided, and a sacrificial layer is formed over the substrate. An opening is patterned through the sacrificial layer, and the opening is filled with conductive material. The sacrificial layer is removed while the conductive material is left in place. A first dielectric layer is formed along sidewalls of the conductive material that was left in place.

公开(公告)号：US09721895B1

公开(公告)日：2017-08-01

申请号：US15287407

申请日：2016-10-06

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang

IPC: H01L21/00 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3213

CPC classification number: H01L21/32134 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/32136 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2221/1036

Abstract: An interconnect dielectric material having an opening formed therein is first provided. A surface nitridation process is then performed to form a nitridized dielectric surface layer within the interconnect dielectric material. A metal layer is formed on the nitridized dielectric surface layer and then an anneal is performed to form a metal nitride layer between the metal layer and the nitridized dielectric surface layer. A portion of the originally deposited metal layer that is not reacted with the nitridized dielectric surface is then selectively removed and thereafter an electrical conducting structure is formed directly on the metal nitride layer that is present in the opening.

公开(公告)号：US09559136B2

公开(公告)日：2017-01-31

申请号：US14618937

申请日：2015-02-10

Applicant: CANON KABUSHIKI KAISHA

Inventor： Aiko Kato ,  Yu Nishimura ,  Hiroaki Naruse ,  Keita Torii

IPC: H01L27/146 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L27/14636 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76808 ,  H01L27/14612 ,  H01L27/1462 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14638 ,  H01L27/14687 ,  H01L2221/1036

Abstract: A semiconductor device manufacturing method includes a step of forming a hole reaching a first insulating layer over a first conductive member; a step of forming a trench reaching a second insulating layer and in communication with the hole; a step of forming an opening exposing the first conductive member in the hole; and a step of forming a second conductive member connected to the first conductive member by embedding a conductive material in the opening, the hole, and the trench. The trench is formed under an etching condition such that the etching rate with respect to the second insulating layer is lower than the etching rate with respect to the third insulating layer.

Abstract translation: 半导体器件制造方法包括在第一导电构件上形成到达第一绝缘层的孔的步骤; 形成到达第二绝缘层并与孔连通的沟槽的步骤; 形成在孔中露出第一导电构件的开口的步骤; 以及通过在开口，孔和沟槽中嵌入导电材料来形成连接到第一导电构件的第二导电构件的步骤。 在蚀刻条件下形成沟槽，使得相对于第二绝缘层的蚀刻速率低于相对于第三绝缘层的蚀刻速率。

公开(公告)号：US09431292B1

公开(公告)日：2016-08-30

申请号：US14698948

申请日：2015-04-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Griselda Bonilla ,  Samuel S. S. Choi ,  Ronald G. Filippi ,  Elbert E. Huang ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76808 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76879 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1036

Abstract: After forming at least one opening in a material stack comprising a sacrificial metal template layer overlying a first dielectric material layer, a sacrificial material portion is deposited in the at least one opening as a place holder for an interconnect structure later formed. Next, the sacrificial metal template layer is removed and a second dielectric material layer is formed to fill voids that were previously occupied by the sacrificial metal template layer. After removing the sacrificial material portion from the at least one opening, an interconnect structure is formed within the at least one opening.

Abstract translation: 在包括覆盖在第一介电材料层上的牺牲金属模板层的材料堆叠中形成至少一个开口之后，牺牲材料部分沉积在所述至少一个开口中，作为稍后形成的互连结构的占位符。 接下来，去除牺牲金属模板层，并且形成第二介电材料层以填充先前被牺牲金属模板层占据的空隙。 在从至少一个开口去除牺牲材料部分之后，在至少一个开口内形成互连结构。

公开(公告)号：US09362239B2

公开(公告)日：2016-06-07

申请号：US14519291

申请日：2014-10-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Oliver Aubel ,  Georg Talut ,  Thomas Werner

IPC: H01L23/52 ,  H01L23/60 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/53214 ,  H01L21/76829 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53219 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53261 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1036 ,  H01L2224/05006 ,  H01L2224/05546

Abstract: The present disclosure relates to a semiconductor structure including a plurality of connecting lines arranged on a plurality of vertical levels, the plurality of connecting lines including at least a first connecting line arranged in a first vertical level and a second connecting line arranged in a second vertical level, different from the first vertical level, and a breakdown prevention layer placed in at least part of the vertical space separating the first connecting line from the second connecting line.

Abstract translation: 本公开涉及包括布置在多个垂直级上的多条连接线的半导体结构，所述多条连接线至少包括布置在第一垂直级中的第一连接线和布置在第二垂直方向上的第二连接线 与第一垂直水平不同的防水层，以及放置在将第一连接线与第二连接线分隔开的垂直空间的至少一部分中的击穿防止层。

公开(公告)号：US09355955B2

公开(公告)日：2016-05-31

申请号：US14701541

申请日：2015-05-01

Applicant: Renesas Electronics Corporation

Inventor： Naohito Suzumura ,  Yoshihiro Oka

IPC: H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/768 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/538 ,  H01L23/5384 ,  H01L24/05 ,  H01L2221/1036 ,  H01L2221/1047 ,  H01L2224/02166 ,  H01L2224/05556 ,  H01L2924/1306 ,  H01L2924/00

Abstract: A semiconductor device is provided in which reliability of the semiconductor device is improved by improving an EM characteristic, a TDDB characteristic, and a withstand voltage characteristic of the semiconductor device. An average diameter of first vacancies in a lower insulating layer which configures an interlayer insulating film of a porous low-k film for embedding a wiring therein, is made smaller than an average diameter of second vacancies in an upper insulating layer, and thereby an elastic modulus is increased in the lower insulating layer. Further, a side wall insulating layer which is a dense layer including the first vacancies having an average diameter smaller than the second vacancies is formed on the surface of the interlayer insulating film exposed on a side wall of a wiring trench.

Abstract translation: 提供一种通过改善半导体器件的EM特性，TDDB特性和耐电压特性来提高半导体器件的可靠性的半导体器件。 使构成用于在其中嵌入布线的多孔低k膜的层间绝缘膜的下绝缘层中的第一空位的平均直径小于上绝缘层中的第二空位的平均直径，从而弹性 下绝缘层的模量增加。 此外，在布线沟槽的侧壁上暴露的层间绝缘膜的表面上形成作为包含平均直径小于第二空位的第一空位的致密层的侧壁绝缘层。