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    Planarization method for fabricating high density semiconductor devices
    101.
    发明授权
    Planarization method for fabricating high density semiconductor devices 失效
    用于制造高密度半导体器件的平面化方法

    公开(公告)号：US5132237A

    公开(公告)日：1992-07-21

    申请号：US647494

    申请日：1991-01-28

    Applicant: James A. Matthews

    Inventor： James A. Matthews

    IPC: H01L21/28 ,  H01L21/285 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/417

    CPC classification number: H01L21/28211 ,  H01L21/28525 ,  H01L21/7688 ,  H01L21/76897 ,  H01L21/8249 ,  H01L29/41708 ,  H01L29/41775 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S148/136

    Abstract: A method for forming a BICMOS integrated circuit having MOS field-effect devices and bipolar junction transistors formed in a silicon substrate is disclosed. The process comprises the steps of first defining separate active areas in a substrate for each of the transistors. Next, a gate dielectric layer is formed over the surface of the wafer. Above the gate dielectric, a first layer of polysilicon is deposited. This first layer of polysilicon is then selectively etched to form a plurality of first polysilicon members each of which is equally-spaced apart from one another. The polysilicon members comprise the gates of the MOS transistors and the extrinsic base contacts of the NPN transistors. After the first polysilicon members have been defined, the base regions of the NPN transistors are formed. After insulating the first polysilicon members, an additional layer of polysilicon is deposited over the substrate to replanarize the entire wafer surface. The additional layer of polysilicon is then etched to form a plurality of second polysilicon members which are electrically isolated from the first polysilicon members. Impurities are diffused from the polysilicon members into the substrate to form the source/drain regions of the MOS transistors, and the extrinsic base and emitter regions of the NPN transistors. The final processing steps include those required for the interconnection of the MOS and NPN transistors.

    Method of making hall effect semiconductor memory cell
    102.
    发明授权
    Method of making hall effect semiconductor memory cell 失效
    制作霍尔效应半导体存储单元的方法

    公开(公告)号：US5075247A

    公开(公告)日：1991-12-24

    申请号：US640061

    申请日：1991-01-11

    Applicant: James A. Matthews

    Inventor： James A. Matthews

    IPC: G11C11/18

    CPC classification number: G11C11/18

    Abstract: A non-volatile, static magnetic memory device, whose operation is based on the Hall effect, is disclosed. The device includes a magnetic patch which stores data in the form of a magnetic field, a semiconductor Hall bar and a pair of integrally-formed bipolar transistors used for amplifying and buffering the Hall voltage produced along the Hall bar. Current is forced to flow down the length of the Hall bar causing a Hall voltage to be developed in a direction transverse to the direction of both the magnetic field and the current. The bases of the bipolar transistors are ohmically coupled to the Hall bar to sense the Hall voltage--the polarity of which is representative of the stored information. A system of current carrying conductors is employed for writing data to individual magnetic patches.

    Abstract translation: 公开了一种基于霍尔效应的非易失性静磁存储器件。 该器件包括以磁场形式存储数据的磁片，半导体霍尔棒和用于放大和缓冲沿着霍尔棒产生的霍尔电压的一对整体形成的双极晶体管。 电流被迫流过霍尔杆的长度，导致霍尔电压在横向于磁场和电流方向的方向上发展。 双极晶体管的基极欧姆耦合到霍尔棒，以感测霍尔电压，其极性代表存储的信息。 使用载流导体的系统将数据写入各个磁性片。

    Configurable cache allowing cache-type and buffer-type access
    110.
    再颁专利
    Configurable cache allowing cache-type and buffer-type access 有权
    可配置缓存允许缓存类型和缓冲区类型访问

    公开(公告)号：USRE43798E1

    公开(公告)日：2012-11-06

    申请号：US11606321

    申请日：2006-11-30

    Applicant: Craig C. Hansen

    Inventor： Craig C. Hansen

    IPC: G06F12/06

    CPC classification number: G06F12/0284 ,  G06F12/1045 ,  G06F12/1491

    Abstract: A virtual memory system including a local-to-global virtual address translator for translating local virtual addresses having associated task specific address spaces into global virtual addresses corresponding to an address space associated with multiple tasks, and a global virtual-to-physical address translator for translating global virtual addresses to physical addresses. Protection information is provided by each of the local virtual-to-global virtual address translator, the global virtual-to-physical address translator, the cache tag storage, or a protection information buffer depending on whether a cache bit or miss occurs during a given data or instruction access. The cache is configurable such that it can be configured into a buffer portion or a cache portion for faster cache accesses.

    Abstract translation: 一种包括本地到全局虚拟地址转换器的虚拟存储器系统，用于将具有相关联的任务特定地址空间的本地虚拟地址转换成对应于与多个任务相关联的地址空间的全局虚拟地址，以及全局虚拟到物理地址转换器， 将全局虚拟地址转换为物理地址。 保护信息由本地虚拟到全局虚拟地址转换器，全局虚拟到物理地址转换器，高速缓存标签存储或保护信息缓冲器中的每一个提供，这取决于在给定的时间段期间是否发生高速缓存位或错误 数据或指令访问。 高速缓存是可配置的，使得其可以被配置为缓存部分或高速缓存部分以用于更快的高速缓存访​​问。

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