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公开(公告)号：US20210184687A1
公开(公告)日：2021-06-17
申请号：US17186180
申请日：2021-02-26
Applicant: Silicon Laboratories Inc.
Inventor： James D. Barnette , William Anker , Xue-Mei Gong
Abstract: A method for operating a clock product includes selectively coupling a first output divider and a second output divider based on a determination of whether the first divider value is integrally related to the second divider value. In response to the first divider value being integrally related to the second divider value, the selectively coupling includes cascading the first output divider with the second output divider. In in response to the first divider value being non-integrally related to the second divider value, the selectively coupling includes configuring the second output divider to be cascaded with a first phase-locked loop and in parallel with the first output divider and to be responsive to an error correction signal based on a difference in response times of the first output divider and the second output divider to a change in a filtered phase difference signal of the first phase-locked loop.
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公开(公告)号：US20210176020A1
公开(公告)日：2021-06-10
申请号：US16707401
申请日：2019-12-09
Applicant: Silicon Laboratories Inc.
IPC: H04L1/20 , G01R31/30 , G01R31/317 , G01R29/26
Abstract: A method for estimating jitter of a clock signal includes generating a phase-adjusted clock signal based on an input clock signal and a feedback clock signal using a frequency-divided clock signal. The method generating N digital time codes for each phase adjustment of P phase adjustments of the phase-adjusted clock signal using a reference clock signal. Each digital time code of the N digital time codes corresponds to a first edge of a clock signal based on the frequency-divided clock signal. P is a first integer greater than zero and N is a second integer greater than zero. The method includes generating a jitter indicator based on an expected period of the clock signal and the N digital time codes for each phase adjustment of the P phase adjustments.
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公开(公告)号：US11032769B2
公开(公告)日：2021-06-08
申请号：US15845813
申请日：2017-12-18
Applicant: Silicon Laboratories Inc.
Inventor： Partha Sarathy Murali , Nagaraja Reddy Anakala , Ajay Mantha
IPC: H04W52/02 , H04W4/80 , H04W4/029 , H04W4/06 , H04W4/70 , H04W84/18 , H04W84/12 , H04L25/02 , H04L27/06
Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.
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公开(公告)号：US20210157355A1
公开(公告)日：2021-05-27
申请号：US16693559
申请日：2019-11-25
Applicant: Silicon Laboratories Inc.
Inventor： Vivek Sarda
Abstract: A data handoff controller includes a counter coupled to supply a count value indicative of a skew between a first clock signal and a second clock signal. The first and second clock signal have a fundamental beat frequency. A greatest common factor circuit is used to determine the fundamental beat frequency and the second is reset based on the beat frequency. A sampling circuit samples first clock domain data with the second clock signal. The sampling circuit is controlled to sample, at least in part, based on the count value. The count value can be used to impose a blackout window in which data is not sampled to avoid sampling data around data transitions of the first clock domain data. The count value can also be used to select an edge of the second clock signal to use for sampling the first clock domain data to ensure first clock domain data is not sampled during data transitions.
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公开(公告)号：US20210150068A1
公开(公告)日：2021-05-20
申请号：US16687959
申请日：2019-11-19
Applicant: Silicon Laboratories Inc.
Inventor： Javier Elenes
Abstract: Embodiments include cryptographic circuits having isolated operation with respect to embedded sensor operations to mitigate side-channel attacks. A cryptographic circuit, a sensor, and an analog-to-digital converter (ADC) circuit are integrated into an integrated circuit along with a cryptographic circuit. A sensed signal is output with the sensor, and the sensed signal is converted to digital data using the ADC circuit. Further, cryptographic data is generated using one or more secret keys and the cryptographic circuit. The generation of the cryptographic data has isolated operation with respect to the operation of the sensor and the ADC circuit. The isolated operation mitigates side-channel attacks. The isolated operation can be achieved using power supply, clock, and/or reset circuits for the cryptographic circuit that are electrically isolated from similar circuits for the sensor and ADC circuit. The isolated operation can also be achieved using time-division multiplex operations. Other variations can also be implemented.
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Patent Agency Ranking
公开(公告)号：US20210141661A1
公开(公告)日：2021-05-13
申请号：US16680915
申请日：2019-11-12
Applicant: Silicon Laboratories Inc.
Inventor： Jean-François Deschenes
Abstract: A system and method of minimizing the context saved when the processing unit is disclosed. The kernel attempts to save time and memory by reducing or eliminating the amount of context that is saved or restored in certain situations. Specifically, if there is no currently executing, the kernel does not save any context before switching to another task. Similarly, if there is no new task to execute, the kernel does not restore any context before making the context switch. Rather, the kernel applies a lightweight context. In some embodiments, the idle context uses the ISR stack rather than having a dedicated stack. This system and method reduces the time required for certain context switches and also saves memory.
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公开(公告)号：US20210135692A1
公开(公告)日：2021-05-06
申请号：US16886645
申请日：2020-05-28
Applicant: Silicon Laboratories Inc.
Inventor： Hendricus de Ruijter , Güner Arslan , Wentao Li , Michael Wu
Abstract: An apparatus comprises an RF receiver for receiving an RF signal. The RF receiver includes front-end circuitry to generate a first down-converted signal, and a plurality of signal detectors to generate a corresponding plurality of detection signals from signals derived from the down-converted signal. The RF receiver further includes a controller to provide at least one control signal to the front-end circuitry based on the plurality of detection signals.
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公开(公告)号：US10972077B2
公开(公告)日：2021-04-06
申请号：US16912652
申请日：2020-06-25
Applicant: Silicon Laboratories Inc.
Inventor： Steffen Skaug , Vitor Pereira , Arup Mukherji
Abstract: An integrated circuit including a functional circuit including at least one swapping circuit node, multiple duplicate electronic circuits, and a switch circuit. The duplicate electronic circuits are integrated in close proximity with each other each including at least one electronic device that is susceptible to RTN. The switch circuit electrically couples a different selected subset of at least one of the duplicate electronic circuits to the at least one swapping circuit node for each of successive switching states during operation of the functional circuit. A method of reducing noise including selecting a subset of the duplicate electronic circuits, electrically coupling the selected duplicate electronic devices to at least one swapping circuit node of a functional circuit, and repeating the selecting and electrically coupling in successive switching states during operation of the functional circuit for different subsets of the duplicate electronic circuits.
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公开(公告)号：US20210080993A1
公开(公告)日：2021-03-18
申请号：US16569991
申请日：2019-09-13
Applicant: Silicon Laboratories Inc.
Inventor： Thomas Saroshan David
IPC: G06F1/08 , H03K17/687
Abstract: A configurable clock buffer including first and second buffers and isolation circuitry. The first buffer has an input coupled to a clock input node and has an output coupled to a clock output node. The second buffer has an input coupled to an intermediate input node and has an output coupled to an intermediate output node. The isolation circuitry is responsive to at least one mode signal, in which it electrically couples the intermediate input node to the clock input node and electrically couples the intermediate output node to the clock output node when the at least one mode signal is in a first state, and in which it electrically couples the intermediate input node to a static node and electrically isolates the intermediate output node from the clock output node when the at least one mode signal is in a second state.
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公开(公告)号：US10917081B1
公开(公告)日：2021-02-09
申请号：US16815435
申请日：2020-03-11
Applicant: Silicon Laboratories Inc.
Inventor： Long Nguyen , Ion C. Tesu , Michael L. Duffy , John N. Wilson
IPC: H03K17/08 , H03K17/0812 , H02M1/08 , H03K17/18 , H03K17/082 , H03K17/081 , H03K17/16
Abstract: An apparatus controls a high-power drive device external to a package of a gate driver circuit. A first circuit charges the control node over a first length of time in response to a first signal through the first node indicating an absence of a fault condition and a first level of a control signal. A second circuit discharges the control node over a second length of time in response to a second signal through the second node indicating the absence of the fault condition and a second level of a control signal. A third circuit includes a current amplifier and is configured as a soft shutdown path to discharge the control node over a third length of time in response to the first signal through the first node indicating a presence of the fault condition. The third length of time is different from the second length of time.
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