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    CHIP SCALE SENSING CHIP PACKAGE AND A MANUFACTURING METHOD THEREOF
    101.
    发明申请
    CHIP SCALE SENSING CHIP PACKAGE AND A MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20170098678A1

    公开(公告)日：2017-04-06

    申请号：US15280959

    申请日：2016-09-29

    Applicant: XINTEC INC.

    Inventor： Chaung-Lin LAI ,  Wei-Ming CHIEN

    IPC: H01L27/146

    CPC classification number: H01L27/14636 ,  H01L27/14618 ,  H01L27/1462 ,  H01L27/14685 ,  H01L27/14687 ,  H01L2224/11

    Abstract: This present invention provides a chip scale sensing chip package, comprising: a sensing chip with a first top surface and a first bottom surface opposite to each other, wherein the first top surface has a first insulating layer formed thereon, and the sensing chip comprises a sensing device adjacent to the first top surface and a plurality of conductive pads formed within the first insulating and adjacent to the sensing device, and a wiring layer formed on the first bottom surface to respectively connect to each of the conductive pads; and a dam formed on the first insulating layer adjacent to the sensing device.

    IMAGE SENSOR CHIP PACKAGE AND FABRICATING METHOD THEREOF
    106.
    发明申请
    IMAGE SENSOR CHIP PACKAGE AND FABRICATING METHOD THEREOF 审中-公开
    图像传感器芯片包装及其制作方法

    公开(公告)号：US20160380024A1

    公开(公告)日：2016-12-29

    申请号：US15261808

    申请日：2016-09-09

    Applicant: XINTEC INC.

    Inventor： Chih-Hao CHEN ,  Bai-Yao LOU ,  Shih-Kuang CHEN

    IPC: H01L27/146

    CPC classification number: H01L27/14687 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14685 ,  H01L27/14698 ,  H01L2224/13

    Abstract: A method for fabricating an image sensor chip package begins at providing a wafer, which includes forming a plurality of image sensor components on a substrate, forming a plurality of spacers on the substrate for separating the image sensor components, and disposing a transparent plate on the spacers. The method further includes forming a plurality of stress notches on the transparent plate. After the stress notches are formed, the transparent plate is pressed and the substrate is cut at the second chambers. The transparent plate is broken along the stress notches.

    Abstract translation: 制造图像传感器芯片封装的方法开始于提供晶片，其包括在基板上形成多个图像传感器部件，在基板上形成多个间隔物以分离图像传感器部件，并将透明板设置在 间隔物 该方法还包括在透明板上形成多个应力凹口。 在形成应力凹口之后，按压透明板并在第二腔室切割基板。 透明板沿着应力凹口断裂。

    IMAGE SENSING DEVICE
    107.
    发明申请
    IMAGE SENSING DEVICE 审中-公开
    图像传感装置

    公开(公告)号：US20160351607A1

    公开(公告)日：2016-12-01

    申请号：US15166261

    申请日：2016-05-27

    Applicant: XINTEC INC.

    Inventor： Tsang-Yu LIU ,  Chi-Chang LIAO

    IPC: H01L27/146

    CPC classification number: H01L27/14618 ,  H01L27/14601 ,  H01L27/14687 ,  H04N5/2253

    Abstract: An image sensing device includes a printed circuit board, a chip package, and an adhesive layer. The printed circuit board has a concave portion. The chip package has a sensing surface and a bonding surface that is opposite to the sensing surface. The adhesive layer is disposed between the bonding surface of the chip package and the concave portion of the printed circuit board. The adhesive layer has an aggregation force. The chip package is bent through a surface of the concave portion and the aggregation force, such that the sensing surface of the chip package is an arc surface.

    Abstract translation: 图像感测装置包括印刷电路板，芯片封装和粘合剂层。 印刷电路板具有凹部。 芯片封装具有感测表面和与感测表面相对的接合表面。 粘合剂层设置在芯片封装的接合表面和印刷电路板的凹部之间。 粘合剂层具有聚集力。 芯片封装通过凹部的表面和聚集力弯曲，使得芯片封装的感测表面是弧形表面。

    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    108.
    发明申请
    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
    半导体结构及其制造方法

    公开(公告)号：US20160329283A1

    公开(公告)日：2016-11-10

    申请号：US15140289

    申请日：2016-04-27

    Applicant: XINTEC INC.

    Inventor： Yu-Tung CHEN ,  Chien-Min LIN ,  Chuan-Jin SHIU ,  Chih-Wei HO ,  Yen-Shih HO

    IPC: H01L23/528 ,  H01L23/00 ,  H01L21/768 ,  H01L21/027 ,  H01L23/522

    CPC classification number: H01L23/5283 ,  H01L21/0271 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0345 ,  H01L2224/0557

    Abstract: A semiconductor structure includes a first substrate, a second substrate, a dam layer, a photoresist layer, and a conductive layer. The first substrate has a conductive pad. The second substrate has a through via, a sidewall surface surrounding the through via, a first surface, and a second surface opposite to the first surface. The through via penetrates through the first and second surfaces. The conductive pad is aligned with the through via. The dam layer is located between the first substrate and the second surface. The dam layer protrudes toward the through via. The photoresist layer is located on the first surface, the sidewall surface, the dam layer protruding toward the through via, and between the conductive pad and the dam layer protruding toward the through via. The conductive layer is located on the photoresist layer and the conductive pad.

    Abstract translation: 半导体结构包括第一基板，第二基板，阻挡层，光致抗蚀剂层和导电层。 第一基板具有导电垫。 第二基板具有通孔，围绕通孔的侧壁表面，第一表面和与第一表面相对的第二表面。 通孔穿过第一和第二表面。 导电垫与通孔对齐。 坝层位于第一基板和第二表面之间。 坝层朝向通孔突出。 光致抗蚀剂层位于第一表面上，侧壁表面，阻挡层朝向通孔突出，并且在导电垫和阻挡层之间朝向通孔突出。 导电层位于光致抗蚀剂层和导电垫上。

    CHIP PACKAGE AND FABRICATION METHOD THEREOF
    109.
    发明申请
    CHIP PACKAGE AND FABRICATION METHOD THEREOF 有权
    芯片包装及其制造方法

    公开(公告)号：US20160322305A1

    公开(公告)日：2016-11-03

    申请号：US15139276

    申请日：2016-04-26

    Applicant: XINTEC INC.

    Inventor： Shih-Yi LEE ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Ho-Yin YIU

    IPC: H01L23/538 ,  H01L23/544 ,  H01L21/48 ,  H01L21/78

    CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/145 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2221/68327 ,  H01L2224/13024 ,  H01L2224/18

    Abstract: A chip package includes a chip, a laser stop layer, a first though hole, an isolation layer, a second though hole and a conductive layer. The laser stop layer is disposed above a first surface of the chip, and the first though hole is extended from a second surface to the first surface of the chip to expose the laser stop layer. The isolation layer is below the second surface and in the first through hole, and the isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the first surface, and the second though hole is through the first through hole to expose the laser stop layer. The conductive layer is disposed below the third surface and extended into the second though hole to contact the laser stop layer.

    Abstract translation: 芯片封装包括芯片，激光停止层，第一通孔，隔离层，第二通孔和导电层。 激光停止层设置在芯片的第一表面之上，并且第一通孔从芯片的第二表面延伸到第一表面以暴露激光停止层。 隔离层位于第二表面下方，在第一通孔中，隔离层具有与第二表面相对的第三表面。 第二通孔从第三表面延伸到第一表面，第二通孔穿过第一通孔以暴露激光停止层。 导电层设置在第三表面下方并延伸到第二通孔中以接触激光停止层。

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