公开(公告)号：US09442025B2

公开(公告)日：2016-09-13

申请号：US14066942

申请日：2013-10-30

Applicant: Apple Inc.

Inventor： Yizhang Yang ,  Jun Zhai

IPC: G01K15/00 ,  G01K3/04 ,  G01K7/01

CPC classification number: G01K15/005 ,  G01K7/01

Abstract: In some embodiments, a method may be provided for calibrating integrated circuit temperature sensors. The method may include sensing a first temperature using a first temperature sensor and a second temperature using a second temperature sensor. The first temperature sensor may be calibrated and is external to a package of the integrated circuit. The second temperature sensor may be included in the integrated circuit. The method may include increasing a temperature of the integrated circuit. The method may include allowing the integrated circuit and the package to thermally equilibrate over a first period of time. The method may include sensing a first slope of a temperature decay by the first temperature sensor. The method may include sensing a second slope of a temperature decay by the second temperature sensor. The method may include calibrating the second temperature sensor responsive to a difference between the first and second temperatures and the first and second slopes.

Abstract translation: 在一些实施例中，可以提供用于校准集成电路温度传感器的方法。 该方法可以包括使用第一温度传感器感测第一温度，并且使用第二温度传感器来感测第二温度。 第一温度传感器可以被校准，并且在集成电路的封装外部。 第二温度传感器可以包括在集成电路中。 该方法可以包括增加集成电路的温度。 该方法可以包括允许集成电路和封装在第一时间段内热平衡。 该方法可以包括感测第一温度传感器的温度衰减的第一斜率。 该方法可以包括感测第二温度传感器的温度衰减的第二斜率。 该方法可以包括响应于第一和第二温度与第一和第二斜率之间的差异来校准第二温度传感器。

公开(公告)号：US20160093592A1

公开(公告)日：2016-03-31

申请号：US14601623

申请日：2015-01-21

Applicant: Apple Inc.

Inventor： Jun Zhai

IPC: H01L25/065 ,  H01L49/02 ,  H01L23/528 ,  H01L23/31 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L21/78

Abstract: A semiconductor device is described that includes an integrated circuit coupled to a first semiconductor substrate with a first set of passive devices (e.g., inductors) on the first substrate. A second semiconductor substrate with a second set of passive devices (e.g., capacitors) may be coupled to the first substrate. Interconnects in the substrates may allow interconnection between the substrates and the integrated circuit. The passive devices may be used to provide voltage regulation for the integrated circuit. The substrates and integrated circuit may be coupled using metallization.

Abstract translation: 描述了一种半导体器件，其包括在第一衬底上与第一组无源器件（例如，电感器）耦合到第一半导体衬底的集成电路。 具有第二组无源器件（例如，电容器）的第二半导体衬底可以耦合到第一衬底。 基板中的互连可以允许基板和集成电路之间的互连。 无源器件可用于为集成电路提供电压调节。 基板和集成电路可以使用金属化来耦合。

公开(公告)号：US20150364454A1

公开(公告)日：2015-12-17

申请号：US14558906

申请日：2014-12-03

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Se Young Yang

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/528 ,  H01L23/31 ,  H01L23/367 ,  H01L25/065 ,  H01L23/522

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/17 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/24137 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

Abstract: In some embodiments, it is desirable to increase memory bandwidth using an integrated solution. In one embodiment, wide I/O memory may be used. Described herein are embodiments of systems and methods of reconfiguring wide I/O memory modules. The reconfigured memory modules may be configured such that the memory modules function in combination with current packaging architectures.

Abstract translation: 在一些实施例中，期望使用集成解决方案来增加存储器带宽。 在一个实施例中，可以使用宽I / O存储器。 这里描述了重新配置宽I / O存储器模块的系统和方法的实施例。 重新配置的存储器模块可以被配置为使得存储器模块与当前的封装体系结合起来。

公开(公告)号：US20150160701A1

公开(公告)日：2015-06-11

申请号：US14097491

申请日：2013-12-05

Applicant: Apple Inc.

Inventor： John Bruno ,  Jun Zhai ,  Timothy J. Millet

IPC: G06F1/18

CPC classification number: H01L25/18 ,  H01L23/13 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/13124 ,  H01L2224/134 ,  H01L2224/13411 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0204 ,  H05K1/141 ,  H05K1/144 ,  H05K1/181 ,  H05K2201/09036 ,  H05K2201/10416 ,  H05K2201/10734 ,  H01L2924/014

Abstract: A semiconductor package includes a processor die (e.g., an SoC) and one or more memory die (e.g., DRAM) coupled to a ball grid array (BGA) substrate. The processor die and the memory die are coupled to opposite sides of the BGA substrate using terminals (e.g., solder balls). The package may be coupled to a printed circuit board (PCB) using one or more terminals positioned around the perimeter of the processor die. The PCB may include a recess with at least part of the processor die being positioned in the recess. Positioning at least part of the processor die in the recess reduces the overall height of the semiconductor package assembly. A voltage regulator may also be coupled to the BGA substrate on the same side as the processor die with at least part of the voltage regulator being positioned in the recess a few millimeters from the processor die.

Abstract translation: 半导体封装包括耦合到球栅阵列（BGA）衬底的处理器管芯（例如，SoC）和一个或多个存储器管芯（例如，DRAM）。 使用端子（例如，焊球）将处理器管芯和存储器管芯耦合到BGA衬底的相对侧。 可以使用位于处理器管芯的周边周围的一个或多个端子将封装耦合到印刷电路板（PCB）。 PCB可以包括凹部，其中处理器管芯的至少一部分位于凹部中。 将处理器管芯的至少一部分定位在凹部中减小了半导体封装组件的整体高度。 电压调节器还可以与处理器管芯相同侧的BGA衬底耦合，其中至少一部分电压调节器位于距离处理器管芯几毫米的凹槽中。

公开(公告)号：US20150117486A1

公开(公告)日：2015-04-30

申请号：US14066942

申请日：2013-10-30

Applicant: Apple Inc.

Inventor： Yizhang Yang ,  Jun Zhai

IPC: G01K15/00 ,  G01K7/01

CPC classification number: G01K15/005 ,  G01K7/01

Abstract: In some embodiments, a method may be provided for calibrating integrated circuit temperature sensors. The method may include sensing a first temperature using a first temperature sensor and a second temperature using a second temperature sensor. The first temperature sensor may be calibrated and is external to a package of the integrated circuit. The second temperature sensor may be included in the integrated circuit. The method may include increasing a temperature of the integrated circuit. The method may include allowing the integrated circuit and the package to thermally equilibrate over a first period of time. The method may include sensing a first slope of a temperature decay by the first temperature sensor. The method may include sensing a second slope of a temperature decay by the second temperature sensor. The method may include calibrating the second temperature sensor responsive to a difference between the first and second temperatures and the first and second slopes.

Abstract translation: 在一些实施例中，可以提供用于校准集成电路温度传感器的方法。 该方法可以包括使用第一温度传感器感测第一温度，并且使用第二温度传感器来感测第二温度。 第一温度传感器可以被校准，并且在集成电路的封装外部。 第二温度传感器可以包括在集成电路中。 该方法可以包括增加集成电路的温度。 该方法可以包括允许集成电路和封装在第一时间段内热平衡。 该方法可以包括感测第一温度传感器的温度衰减的第一斜率。 该方法可以包括感测第二温度传感器的温度衰减的第二斜率。 该方法可以包括响应于第一和第二温度与第一和第二斜率之间的差异来校准第二温度传感器。

公开(公告)号：US20140361395A1

公开(公告)日：2014-12-11

申请号：US14294903

申请日：2014-06-03

Applicant: Apple Inc.

Inventor： Milind S. Bhagavat ,  Jun Zhai

IPC: H01L27/146 ,  G06K9/00

CPC classification number: G06K9/0002 ,  H01L27/14634 ,  H01L27/14636

Abstract: A sensor includes a sensor array formed on a first side of a substrate and at least one circuit operative to communicate with the sensor array formed on a second side of the substrate. At least one via extends through the substrate to electrically connect the sensor array to the at least one circuit. Placing the at least one circuit on the second side of the substrate allows the sensor array to occupy substantially all of the first side of the substrate.

Abstract translation: 传感器包括形成在基板的第一侧上的传感器阵列和至少一个可操作地与形成在基板的第二侧上的传感器阵列通信的电路。 至少一个通孔延伸穿过衬底以将传感器阵列电连接到至少一个电路。 将至少一个电路放置在基板的第二侧上，使得传感器阵列基本上占据基板的所有第一侧。

公开(公告)号：US20140210107A1

公开(公告)日：2014-07-31

申请号：US13753027

申请日：2013-01-29

Applicant: APPLE INC.

Inventor： Jun Zhai

IPC: H01L23/498 ,  H01L21/50

CPC classification number: H01L23/498 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49861 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/03 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/0665

Abstract: A top package used in a PoP (package-on-package) package includes two memory die stacked with a redistribution layer (RDL) between the die. The first memory die is encapsulated in an encapsulant and coupled to a top surface of the RDL. A second memory die is coupled to a bottom surface of the RDL. The second memory die is coupled to the RDL with either a capillary underfill material or a non-conductive paste. The RDL includes routing between each of the memory die and one or more terminals coupled to the RDL on a periphery of the die.

Abstract translation: 在PoP（封装封装）封装中使用的顶级封装包括两个在管芯之间堆叠有再分配层（RDL）的存储器管芯。 第一个存储器管芯封装在密封剂中并耦合到RDL的顶部表面。 第二存储器管芯耦合到RDL的底表面。 第二个存储器管芯使用毛细管底部填充材料或非导电浆料与RDL耦合。 RDL包括在每个存储管芯与耦合到管芯周边上的RDL的一个或多个端子之间的布线。

公开(公告)号：US20250157991A1

公开(公告)日：2025-05-15

申请号：US19023053

申请日：2025-01-15

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu ,  Vidhya Ramachandran

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/66 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/48 ,  H01L23/60 ,  H01L25/00

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

公开(公告)号：US12261132B2

公开(公告)日：2025-03-25

申请号：US18485709

申请日：2023-10-12

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Sanjay Dabral ,  SivaChandra Jangam ,  Jun Zhai ,  Kunzhong Hu

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/544 ,  H01L23/58

Abstract: Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.

公开(公告)号：US20250014960A1

公开(公告)日：2025-01-09

申请号：US18348934

申请日：2023-07-07

Applicant: Apple Inc.

Inventor： Jiongxin LU ,  Kunzhong Hu ,  Jun Zhai

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: Various embodiments of an integrated circuit (IC) die package are disclosed. An IC die package includes an IC die, an interposer structure electrically connected to the IC die, a first bonding structure, a second bonding structure, and a molding compound layer. The first bonding structure includes a first dielectric layer disposed on the IC die and a first conductive plug disposed in the first dielectric layer. The second bonding structure includes a second dielectric layer disposed on the interposer structure and a second conductive plug disposed in the second dielectric layer. The molding compound layer includes a mold region and a mold cavity.