公开(公告)号：US09754930B2

公开(公告)日：2017-09-05

申请号：US15292409

申请日：2016-10-13

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Akram A. Salman

IPC: H01L27/02 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66 ,  H01L29/74 ,  H01L23/528

CPC classification number: H01L27/0262 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823892 ,  H01L23/5283 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/66371 ,  H01L29/742

Abstract: An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base layer is formed by implanting p-type dopants using an implant mask which has a cutout mask element over the base area, so as to block the p-type dopants from the base area. The base layer is implanted concurrently with p-type body wells under NMOS transistors in logic components in the integrated circuit. Subsequent anneals cause the p-type dopants to diffuse into the base area, forming a base with a lower doping density that adjacent regions of the body well of the NMOS transistor in the NMOS SCR. The NMOS SCR may have a symmetric transistor, a drain extended transistor, or may be a bidirectional NMOS SCR with a symmetric transistor integrated with a drain extended transistor.

公开(公告)号：US20170084738A1

公开(公告)日：2017-03-23

申请号：US15364971

申请日：2016-11-30

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Henry Litzmann Edwards

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/7816 ,  H01L27/092 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/42356 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7831 ,  H01L29/7835

Abstract: RESURF-based dual-gate p-n bimodal conduction laterally diffused metal oxide semiconductors (LDMOS). In an illustrative embodiment, a p-type source is electrically coupled to an n-type drain. A p-type drain is electrically coupled to an n-type source. An n-type layer serves as an n-type conduction channel between the n-type drain and the n-type source. A p-type top layer is disposed at the surface of the substrate of said semiconductor device and is disposed above and adjacent to the n-type layer. The p-type top layer serves as a p-type conduction channel between the p-type source and the p-type drain. An n-gate controls current flow in the n-type conduction channel, and a p-gate controls current flow in the p-type conduction channel.

公开(公告)号：US09583612B1

公开(公告)日：2017-02-28

申请号：US15003776

申请日：2016-01-21

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Binghua Hu ,  James Robert Todd

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L29/402 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/32 ,  H01L21/324 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/0617 ,  H01L27/088 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/408 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7823 ,  H01L29/7835

Abstract: An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region. Dopants are implanted into the substrate under the first opening. Subsequently, dielectric sidewalls are formed along a lateral boundary of the first opening. A field relief oxide is formed by thermal oxidation in the area of the first opening exposed by the dielectric sidewalls. The implanted dopants are diffused into the substrate to form the drift region, extending laterally past the layer of field relief oxide. The dielectric sidewalls and layer of oxide mask are removed after the layer of field relief oxide is formed. A gate is formed over a body of the field-plated FET and over the adjacent drift region. A field plate is formed immediately over the field relief oxide adjacent to the gate.

Abstract translation: 包括场致电FET的集成电路通过在氧化物掩模层中形成第一开口而形成，暴露漂移区域的区域。 在第一开口下将掺杂剂注入到基底中。 随后，沿着第一开口的横向边界形成电介质侧壁。 通过在由电介质侧壁暴露的第一开口的区域中的热氧化形成磁场消除氧化物。 注入的掺杂剂扩散到衬底中以形成漂移区域，横向延伸穿过氧化膜层。 在形成磁场释放氧化物层之后，去除电介质侧壁和氧化物掩模层。 栅极形成在场放电的FET的主体上并在相邻漂移区上方。 在与栅极相邻的磁场浮雕氧化物的正上方形成有场板。

公开(公告)号：US09543430B2

公开(公告)日：2017-01-10

申请号：US14531797

申请日：2014-11-03

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards

IPC: H01L29/15 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L23/482 ,  H01L23/528

CPC classification number: H01L29/7816 ,  H01L23/4824 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/53209 ,  H01L27/088 ,  H01L29/0642 ,  H01L29/0696 ,  H01L29/41758 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power transistor includes multiple substantially parallel transistor fingers, where each finger includes a conductive source stripe and a conductive drain stripe. The power transistor also includes multiple substantially parallel conductive connection lines, where each conductive connection line connects at least one source stripe to a common source connection or at least one drain stripe to a common drain connection. The conductive connection lines are disposed substantially perpendicular to the transistor fingers. At least one of the source or drain stripes is segmented into multiple portions, where adjacent portions are separated by a cut location having a higher electrical resistance than remaining portions of the at least one segmented source or drain stripe.

Abstract translation: 功率晶体管包括多个基本上平行的晶体管指状物，其中每个指状物包括导电源极条和导电漏极条纹。 功率晶体管还包括多个基本上平行的导电连接线，其中每个导电连接线将至少一个源条连接到公共源连接或至少一个漏极条连接至公共漏极连接。 导电连接线基本上垂直于晶体管指状物设置。 源极或漏极条纹中的至少一个被分割成多个部分，其中相邻部分被具有比所述至少一个分段源极或漏极条纹的剩余部分更高的电阻的切割位置分开。

公开(公告)号：US09543299B1

公开(公告)日：2017-01-10

申请号：US14861912

申请日：2015-09-22

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Henry Litzmann Edwards

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/7816 ,  H01L27/092 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/42356 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7831 ,  H01L29/7835

Abstract: RESURF-based dual-gate p-n bimodal conduction laterally diffused metal oxide semiconductors (LDMOS). In an illustrative embodiment, a p-type source is electrically coupled to an n-type drain. A p-type drain is electrically coupled to an n-type source. An n-type layer serves as an n-type conduction channel between the n-type drain and the n-type source. A p-type top layer is disposed at the surface of the substrate of said semiconductor device and is disposed above and adjacent to the n-type layer. The p-type top layer serves as a p-type conduction channel between the p-type source and the p-type drain. An n-gate controls current flow in the n-type conduction channel, and a p-gate controls current flow in the p-type conduction channel.

Abstract translation: 基于RESURF的双栅p-n双峰传导横向扩散金属氧化物半导体（LDMOS）。 在说明性实施例中，p型源电耦合到n型漏极。 p型漏极电耦合到n型源极。 n型层用作n型漏极和n型源极之间的n型导电沟道。 p型顶层设置在所述半导体器件的衬底的表面上，并且设置在n型层的上方并与其相邻。 p型顶层用作p型源极和p型漏极之间的p型导电沟道。 n栅极控制n型导电沟道中的电流，p栅极控制p型导电沟道中的电流。

公开(公告)号：US09496313B2

公开(公告)日：2016-11-15

申请号：US14292198

申请日：2014-05-30

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Toan Tran ,  Jeffrey R. Debord ,  Ashesh Parikh ,  Bradley David Sucher

IPC: H01L29/66 ,  H01L27/16 ,  H01L35/04 ,  H01L21/265 ,  H01L27/06 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/16 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823878 ,  H01L27/0617 ,  H01L27/092 ,  H01L29/34 ,  H01L35/04 ,  H01L35/32 ,  H01L35/34

Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between the CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

Abstract translation: 通过在CMOS晶体管之间和嵌入式热电元件的热电元件之间同时形成衬底中的隔离沟槽，形成包含CMOS晶体管和嵌入式热电元件的集成电路。 介电材料形成在隔离沟槽中，以提供横向隔离CMOS晶体管和热电元件的场氧化物。 在用于热电元件的区域中将锗植入衬底中，并且随后对衬底进行退火，以在隔离沟槽之间的热电元件中提供至少0.10原子％的锗密度。 在形成隔离沟槽之后，在形成隔离沟槽之后并且在隔离沟槽内形成电介质材料之前和/或在隔离沟槽中形成电介质材料之后，可以注入锗。

公开(公告)号：US20160126349A1

公开(公告)日：2016-05-05

申请号：US14531797

申请日：2014-11-03

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards

IPC: H01L29/78 ,  H01L29/06 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L29/417

CPC classification number: H01L29/7816 ,  H01L23/4824 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/53209 ,  H01L27/088 ,  H01L29/0642 ,  H01L29/0696 ,  H01L29/41758 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power transistor includes multiple substantially parallel transistor fingers, where each finger includes a conductive source stripe and a conductive drain stripe. The power transistor also includes multiple substantially parallel conductive connection lines, where each conductive connection line connects at least one source stripe to a common source connection or at least one drain stripe to a common drain connection. The conductive connection lines are disposed substantially perpendicular to the transistor fingers. At least one of the source or drain stripes is segmented into multiple portions, where adjacent portions are separated by a cut location having a higher electrical resistance than remaining portions of the at least one segmented source or drain stripe.

Abstract translation: 功率晶体管包括多个基本上平行的晶体管指状物，其中每个指状物包括导电源极条和导电漏极条纹。 功率晶体管还包括多个基本上平行的导电连接线，其中每个导电连接线将至少一个源条连接到公共源连接或至少一个漏极条连接至公共漏极连接。 导电连接线基本上垂直于晶体管指状物设置。 源极或漏极条纹中的至少一个被分割成多个部分，其中相邻部分被具有比所述至少一个分段源极或漏极条纹的剩余部分更高的电阻的切割位置分开。

公开(公告)号：US20160126234A1

公开(公告)日：2016-05-05

申请号：US14531751

申请日：2014-11-03

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards

IPC: H01L27/02 ,  H01L29/45 ,  H01L29/417 ,  H01L21/8222 ,  H01L27/06

CPC classification number: H01L27/0664 ,  H01L21/8222 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/067 ,  H01L29/0649 ,  H01L29/41708 ,  H01L29/45

Abstract: A transistor includes an emitter of a first conductivity type, base of a second conductivity type, collector of the first conductivity type, and cathode of a lateral suppression diode. The emitter is disposed at a top surface of the transistor and configured to receive electrical current from an external source. The base is configured to conduct the electrical current from the collector to the emitter. The base is disposed at the top surface of the transistor and laterally between the emitter and the collector. The collector is configured to attract and collect minority carriers from the base. The cathode of the first conductivity type is surrounded by the base and disposed between the emitter and the collector, and the cathode is configured to suppress a lateral flow of the minority carriers from the base to the collector.

Abstract translation: 晶体管包括第一导电类型的发射极，第二导电类型的基极，第一导电类型的集电极和横向抑制二极管的阴极。 发射极设置在晶体管的顶表面并被配置为从外部源接收电流。 基座被配置为将电流从集电器传导到发射极。 基极设置在晶体管的顶表面，并且在发射极和集电极之间。 收集器被配置为从基地吸引和收集少数载体。 第一导电类型的阴极由基极围绕并且设置在发射极和集电极之间，并且阴极被配置为抑制少数载流子从基极到集电极的横向流动。

公开(公告)号：US20150371985A1

公开(公告)日：2015-12-24

申请号：US14311205

申请日：2014-06-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann Edwards ,  Akram A. Salman ,  Md Iqbal Mahmud

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/747

CPC classification number: H01L27/0262 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/456 ,  H01L29/66386 ,  H01L29/7436 ,  H01L29/747

Abstract: A first silicon controlled rectifier has a breakdown voltage in a first direction and a breakdown voltage in a second direction. A second silicon controlled rectifier has a breakdown voltage with a higher magnitude than the first silicon controlled rectifier in the first direction, and a breakdown voltage with a lower magnitude than the first silicon controlled rectifier in the second direction. A bidirectional electrostatic discharge (ESD) structure utilizes both the first silicon controlled rectifier and the second silicon controlled rectifier to provide bidirectional protection.

Abstract translation: 第一可控硅整流器具有在第一方向上的击穿电压和在第二方向上的击穿电压。 第二可控硅整流器具有在第一方向上具有比第一可控硅整流器更高的幅度的击穿电压，以及在第二方向上具有比第一可控硅整流器更低的幅度的击穿电压。 双向静电放电（ESD）结构利用了第一个可控硅整流器和第二个可控硅整流器来提供双向保护。

公开(公告)号：US20150349023A1

公开(公告)日：2015-12-03

申请号：US14292281

申请日：2014-05-30

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey R. Debord ,  Henry Litzmann Edwards ,  Kenneth J. Maggio

IPC: H01L27/16 ,  H01L21/768 ,  H01L21/8238 ,  H01L35/04 ,  H01L27/092

CPC classification number: H01L27/16 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76879 ,  H01L21/823878 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/0617 ,  H01L27/092 ,  H01L35/04 ,  H01L35/30 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming active areas which provide transistor active areas for an NMOS transistor and a PMOS transistor of the CMOS transistors and provide n-type thermoelectric elements and p-type thermoelectric elements of the embedded thermoelectric device. Stretch contacts with lateral aspect ratios greater than 4:1 are formed over the n-type thermoelectric elements and p-type thermoelectric elements to provide electrical and thermal connections through metal interconnects to a thermal node of the embedded thermoelectric device. The stretch contacts are formed by forming contact trenches in a dielectric layer, filling the contact trenches with contact metal and subsequently removing the contact metal from over the dielectric layer. The stretch contacts are formed concurrently with contacts to the NMOS and PMOS transistors.

Abstract translation: 可以通过形成有源区域来形成包含CMOS晶体管和嵌入式热电装置的集成电路，该有源区域为CMOS晶体管的NMOS晶体管和PMOS晶体管提供晶体管有源区，并提供n型热电元件和p型热电元件 嵌入式热电装置。 在n型热电元件和p型热电元件上形成横截面比大于4:1的拉伸接触，以通过金属互连提供到嵌入式热电器件的热节点的电连接和热连接。 拉伸接触通过在电介质层中形成接触沟槽，用接触金属填充接触沟槽并随后从电介质层上方去除接触金属而形成。 拉伸触点与NMOS和PMOS晶体管的触点同时形成。