公开(公告)号：US11770624B2

公开(公告)日：2023-09-26

申请号：US18072813

申请日：2022-12-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Shashank Dabral ,  Rajasekhar Allu ,  Niraj Nandan

IPC: H04N5/235 ,  H04N9/04 ,  H04N1/60 ,  H04N23/84 ,  G06T1/20 ,  H04N9/67

CPC classification number: H04N23/843 ,  G06T1/20 ,  H04N9/67 ,  H04N2209/046

Abstract: An image signal processor includes a first matrix processing circuit, a post processing circuit, a second matrix processing circuit, and a split visual and analytics circuit. The first matrix processing circuit is configured to receive a plurality of component images generated based on an image captured by an image sensor and generate a plurality of first matrix outputs based on the plurality of component images. The post processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a first luminance component of the image and a chrominance component of the image. The second matrix processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a second luminance component of the image and a saturation component of the image. The split visual and analytics circuit is configured to generate visual and analytic data of the image.

公开(公告)号：US20230239585A1

公开(公告)日：2023-07-27

申请号：US18194762

申请日：2023-04-03

Applicant: Texas Instruments Incorporated

Inventor： Gang Hua ,  Shashank Dabral ,  Mihir Narendra Mody ,  Rajasekhar Reddy Allu ,  Niraj Nandan

IPC: G06T9/00 ,  H04N9/78

CPC classification number: H04N23/88 ,  H04N9/78 ,  H04N23/71 ,  H04N23/76 ,  H04N23/741

Abstract: Local automatic white balance (AWB) of wide dynamic range (WDR) images is provided. Methods and systems include collecting, by an image signal processor (ISP), statistics for local AWB from at least one wide dynamic range (WDR) image received by the ISP; generating, by a processor, based on the statistics, local gain lookup tables (LUTs), one for each color channel represented in the WDR image(s), each local gain LUT providing a correlation between gain and intensity; and storing the local gain LUTs. Further processing includes, for each of multiple pixels of a WDR image to be output calculating an intensity value, accessing the local gain LUT for the color channel corresponding to that pixel using the calculated intensity value to identify a corresponding local gain value, and applying the local gain value to that pixel.

公开(公告)号：US11693795B2

公开(公告)日：2023-07-04

申请号：US17138740

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Mihir Mody ,  Rajat Sagar

IPC: G06F13/28 ,  G06F13/16

CPC classification number: G06F13/1668 ,  G06F13/28

Abstract: Methods and apparatus to extend local buffer of a hardware accelerator are disclosed herein. In some examples, an apparatus, including a local memory, a first hardware accelerator (HWA), a second HWA, the second HWA and the first HWA connected in a flexible data pipeline, and a spare scheduler to manage, in response to the spare scheduler inserted in the flexible data pipeline, data movement between the first HWA and the second HWA through the local memory and a memory. Local buffer extension may be performed by software to control data movement between local memory and other system memory. The other system memory may be on-chip memory and/or external memory. The HWA sub-system includes a set of spare schedulers to manage the data movement. Data aggregation may be performed in the other system memory. Additionally, the other system memory may be utilized for conversion between data line and data block.

公开(公告)号：US11630701B2

公开(公告)日：2023-04-18

申请号：US16377966

申请日：2019-04-08

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Hetul Sanghvi ,  Mihir Narendra Mody

IPC: G06F13/14 ,  G06F9/50 ,  G06F9/48 ,  G06F9/52 ,  G06F9/54 ,  G06T1/20 ,  G06F5/12 ,  G06F13/16 ,  G06F15/78 ,  G06F13/28 ,  G06F13/40 ,  G06F11/07

Abstract: A hardware thread scheduler (HTS) is provided for a multiprocessor system. The HTS is configured to schedule processing of multiple threads of execution by resolving data dependencies between producer modules and consumer modules for each thread. Pattern adaptors may be provided in the scheduler that allows mixing of multiple data patterns across blocks of data. Transaction aggregators may be provided that allow re-using the same image data by multiple threads of execution while the image date remains in a given data buffer. Bandwidth control may be provided using programmable delays on initiation of thread execution. Failure and hang detection may be provided using multiple watchdog timers.

公开(公告)号：US11620757B2

公开(公告)日：2023-04-04

申请号：US17533256

申请日：2021-11-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hetul Sanghvi ,  Mihir Narendra Mody ,  Niraj Nandan ,  Anish Reghunath ,  Michael Peter Lachmayr

IPC: G06T7/20 ,  G06T7/246 ,  G06T7/269

Abstract: A computer vision system is provided that includes an image generation device configured to generate consecutive two dimensional (2D) images of a scene, and a dense optical flow engine (DOFE) configured to determine a dense optical flow map for pairs of the consecutive 2D images, wherein, for a pair of consecutive 2D images, the DOFE is configured to perform a predictor based correspondence search for each paxel in a current image of the pair of consecutive 2D images, wherein, for an anchor pixel in each paxel, the predictor based correspondence search evaluates a plurality of predictors to select a best matching pixel in a reference image of the pair of consecutive 2D images, and determine optical flow vectors for each pixel in a paxel based on the best matching pixel selected for the anchor pixel of the paxel.

公开(公告)号：US11611764B2

公开(公告)日：2023-03-21

申请号：US17330840

申请日：2021-05-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hideo Tamama

IPC: H04N19/176 ,  H04N19/14 ,  H04N19/82 ,  H04N19/86 ,  H04N19/117 ,  H04N19/186

Abstract: A method of de-blocking filtering a processed video is provided. The processed video includes a plurality of blocks and each block includes a plurality of sub-blocks. A current block of the plurality of blocks includes vertical edges and horizontal edges. The processed video further includes a set of control parameters and reconstructed pixels corresponding to the current block. A boundary strength index is estimated at the vertical edges and at the horizontal edges of the current block. The set of control parameters, the reconstructed pixels corresponding to the current block and partially filtered pixels corresponding to a set of adjacent sub-blocks are loaded. The vertical edges and the horizontal edges of the current block are filtered based on the boundary strength index and the set of control parameters such that a vertical edge of the current block is filtered before filtering at least one horizontal edge of the current block.

公开(公告)号：US11537299B2

公开(公告)日：2022-12-27

申请号：US17233361

申请日：2021-04-16

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Rajasekhar Reddy Allu

IPC: G06F3/06 ,  G06F13/28

Abstract: An integrated circuit includes: a local memory; and a first processing circuit coupled to the local memory. The first processing component is configured to: receive a first set of image data; perform a first image processing operation on the first set of image data to produce a second set of image data; and store at least some of the second set of image data into the local memory. The integrated circuit also includes a second processing circuit coupled to the local memory and configured to: receive at least some of the second set of image data from the local memory; and perform a second image processing operation on the second set of image data to produce a third set of image data.

公开(公告)号：US11445207B2

公开(公告)日：2022-09-13

申请号：US16714837

申请日：2019-12-16

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Mihir Narendra Mody ,  Niraj Nandan ,  Mahesh Madhukar Mehendale ,  Subrangshu Das ,  Dipan Kumar Mandal ,  Nainala Vyagrheswarudu ,  Vijayavardhan Baireddy ,  Pavan Venkata Shastry

IPC: H04N11/02 ,  H04N19/43 ,  H04N19/51

Abstract: A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame.

公开(公告)号：US11237991B2

公开(公告)日：2022-02-01

申请号：US16995364

申请日：2020-08-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Mody ,  Niraj Nandan ,  Hetul Sanghvi ,  Brian Chae ,  Rajasekhar Reddy Allu ,  Jason A. T. Jones ,  Anthony Lell ,  Anish Reghunath

IPC: G06F13/16 ,  G06T1/20 ,  H04N5/765 ,  G06F13/28

Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.

公开(公告)号：US20210326276A1

公开(公告)日：2021-10-21

申请号：US17138740

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Mihir Mody ,  Rajat Sagar

IPC: G06F13/16 ,  G06F13/28

Abstract: Methods and apparatus to extend local buffer of a hardware accelerator are disclosed herein. In some examples, an apparatus, including a local memory, a first hardware accelerator (HWA), a second HWA, the second HWA and the first HWA connected in a flexible data pipeline, and a spare scheduler to manage, in response to the spare scheduler inserted in the flexible data pipeline, data movement between the first HWA and the second HWA through the local memory and a memory. Local buffer extension may be performed by software to control data movement between local memory and other system memory. The other system memory may be on-chip memory and/or external memory. The HWA sub-system includes a set of spare schedulers to manage the data movement. Data aggregation may be performed in the other system memory. Additionally, the other system memory may be utilized for conversion between data line and data block.