公开(公告)号：US09134003B2

公开(公告)日：2015-09-15

申请号：US13493330

申请日：2012-06-11

Applicant: Takashi Inoue ,  Tetsuya Suzuki ,  Akihiro Matsumoto ,  Naoki Sone ,  Takanori Namba ,  Hidetada Tanaka

Inventor： Takashi Inoue ,  Tetsuya Suzuki ,  Akihiro Matsumoto ,  Naoki Sone ,  Takanori Namba ,  Hidetada Tanaka

IPC: F21V21/00 ,  F21S8/10

CPC classification number: F21V29/763 ,  F21S41/147 ,  F21S41/192 ,  F21S45/43 ,  F21S45/47 ,  F21S45/49 ,  F21V19/0025

Abstract: In an automotive headlamp, a light-emitting module is configured such that a light-emitting element and a control circuit unit for controlling the lighting of the light-emitting element are structured integrally with each other. A control circuit unit in a position anterior to the light-emitting element in a lamp unit is located below a shade section so that the control circuit unit can be clear of the path of light used to form a low beam light distribution pattern of the light emitted by the light-emitting element. In this setting, the light-emitting element is so located that a main optical axis Ax2 is perpendicular respect to an optical axis Ax1 of the lamp unit and that a light-emitting portion of the light-emitting element protrudes higher than the control circuit unit in the direction of the main optical axis Ax2.

Abstract translation: 在汽车前照灯中，发光模块被配置为使得用于控制发光元件的点亮的发光元件和控制电路单元彼此一体地构造。 在灯单元中位于发光元件前方的位置处的控制电路单元位于阴影部分的下方，使得控制电路单元可以清除用于形成光的近光配光图案的光的路径 由发光元件发射。 在这种情况下，发光元件的位置使得主光轴Ax2相对于灯单元的光轴Ax1垂直，并且发光元件的发光部分比控制电路单元突出 在主光轴Ax2的方向上。

公开(公告)号：US09123739B2

公开(公告)日：2015-09-01

申请号：US13548078

申请日：2012-07-12

Applicant: Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Hironobu Miyamoto

Inventor： Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Hironobu Miyamoto

IPC: H01L29/778 ,  H01L29/78 ,  H01L29/737 ,  H01L29/66 ,  H01L29/423 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed over the first nitride semiconductor layer; and a gate electrode facing the second nitride semiconductor layer via a gate insulating film. Because the second nitride semiconductor layer is formed by stacking plural semiconductor layers with their Al composition ratios different from each other, the Al composition ratio of the second nitride semiconductor layer changes stepwise. The semiconductor layers forming the second nitride semiconductor layer are polarized in the same direction so that, among the semiconductor layers, a semiconductor layer nearer to the gate electrode has higher (or lower) intensity of polarization. In other words, the intensities of polarization of the semiconductor layers change with an inclination based on their distances from the gate electrode so that, at each interface between two semiconductor layers, the amount of negative charge becomes larger than that of positive charge.

Abstract translation: 半导体器件包括：第一氮化物半导体层; 形成在第一氮化物半导体层上的第二氮化物半导体层; 以及经由栅极绝缘膜与第二氮化物半导体层相对的栅电极。 由于第二氮化物半导体层通过堆叠其Al组成比彼此不同的多个半导体层而形成，所以第二氮化物半导体层的Al组成比逐步变化。 形成第二氮化物半导体层的半导体层在相同的方向上极化，使得在半导体层中，更靠近栅电极的半导体层具有较高（或更低）的极化强度。 换句话说，半导体层的极化强度随着与栅电极的距离的倾斜而变化，使得在两个半导体层之间的每个界面处，负电荷的量变得大于正电荷的量。

公开(公告)号：US08853666B2

公开(公告)日：2014-10-07

申请号：US12159599

申请日：2006-10-25

Applicant: Takashi Inoue ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Murase ,  Kazuki Ota ,  Hironobu Miyamoto ,  Katsumi Yamanoguchi ,  Naotaka Kuroda ,  Akio Wakejima ,  Yasuhiro Okamoto

Inventor： Takashi Inoue ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Murase ,  Kazuki Ota ,  Hironobu Miyamoto ,  Katsumi Yamanoguchi ,  Naotaka Kuroda ,  Akio Wakejima ,  Yasuhiro Okamoto

IPC: H01L29/06 ,  H01L29/15 ,  H01L29/778 ,  H01L29/423 ,  H01L29/20

CPC classification number: H01L29/7783 ,  H01L29/0607 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/7787

Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer). To gate length Lg of a FET to be prepared, a sum a of layer thicknesses of an electron supply layer and a channel layer is selected so as to fulfill Lg/a≧5, and in such a case, the layer thickness of the channel layer is selected in a range of not exceeding 5 times (about 500 Å) as long as a de Broglie wavelength of two-dimensional electron gas accumulated in the channel layer in room temperature.

Abstract translation: 在III族氮化物型场效应晶体管中，本发明通过缓冲层中的残留载流子的传导来减少漏电流成分，并且可以实现击穿电压的提高，并提高载流子限制效应（载流子限制） 提高夹断特性的通道（抑制短路效应）。 例如，当将本发明应用于GaN型场效应晶体管时，除了沟道层的GaN之外，使用其中铝组成逐渐或逐步朝向顶部的组分调制（组成梯度）AlGaN层用作 缓冲层（杂质缓冲液）。 对于要制备的FET的栅极长度Lg，选择电子供给层和沟道层的层厚度的和a以满足Lg /a≥5，并且在这种情况下，沟道的层厚度 只要在室温下积聚在通道层中的二维电子气的德布罗意波长，不超过5倍（约500）的范围内选择层。

公开(公告)号：US20140212974A1

公开(公告)日：2014-07-31

申请号：US14128089

申请日：2012-06-22

Applicant: Yasuo Yoshimoto ,  Kentaro Kamimae ,  Yuki Tanabe ,  Taku Oguni ,  Takashi Inoue ,  Tsutomu Mochizuki ,  Makoto Hirama ,  Teruo Fujii ,  Hiroshi Kimura ,  Hideto Tozawa

Inventor： Yasuo Yoshimoto ,  Kentaro Kamimae ,  Yuki Tanabe ,  Taku Oguni ,  Takashi Inoue ,  Tsutomu Mochizuki ,  Makoto Hirama ,  Teruo Fujii ,  Hiroshi Kimura ,  Hideto Tozawa

IPC: C12N5/00 ,  B05D1/00

CPC classification number: B05D1/60 ,  C12M23/20 ,  C12M25/02 ,  C12N5/0068 ,  C12N2533/30

Abstract: Provided is: a cell culture membrane, which is free from materials derived from living organisms, can easily be industrially mass-produced, exhibits superior long-term storage properties and chemical resistance, has excellent cell adhesion properties and long-term culture properties and is capable of replicating a cell adhesion morphology that is similar to that of collagen derived from living organisms and being used for conventional cell cultivation. Also provided are a cell culture substrate, and a method for manufacturing the cell culture substrate. In the present invention, as a cell adhesion layer, a polymer membrane represented by formula (I) is formed on the base of a cell culture substrate so as to have a membrane thickness equal to or greater than 0.2 μm (in the formula, R1 and R2 represent a —(CH2)n—NH2 moiety (n is an integer of 1-10 inclusive.) or H, with at least one of R1 and R2 being a —(CH2)n—NH2 moiety. Moreover, l and m are positive integers expressing polymerization degree).

Abstract translation: 提供：不含活体的物质的细胞培养膜可以容易地在工业上批量生产，具有优异的长期保存性和耐化学性，具有优异的细胞粘附性和长期培养性，并且是 能够复制与来自活生物体的胶原相似的细胞粘附形态，并用于常规细胞培养。 还提供了细胞培养基质和细胞培养基质的制造方法。 在本发明中，作为细胞粘附层，在细胞培养基材的基材上形成由式（I）表示的聚合物膜，以使膜厚等于或大于0.2μm（式中，R1 并且R 2表示 - （CH 2）n -NH 2部分（n是包括1-10的整数）或H，其中R 1和R 2中的至少一个是 - （CH 2）n -NH 2部分，此外， m是表示聚合度的正整数）。

公开(公告)号：US08635710B2

公开(公告)日：2014-01-21

申请号：US13446279

申请日：2012-04-13

Applicant: Toshihiko Nakata ,  Masahiro Watanabe ,  Takashi Inoue ,  Kishio Hidaka ,  Makoto Okai ,  Toshiaki Morita ,  Motoyuki Hirooka

Inventor： Toshihiko Nakata ,  Masahiro Watanabe ,  Takashi Inoue ,  Kishio Hidaka ,  Makoto Okai ,  Toshiaki Morita ,  Motoyuki Hirooka

IPC: G01B11/14 ,  G01Q60/06

CPC classification number: G01Q60/06 ,  G01N21/648 ,  G01Q60/22 ,  G01Q70/12

Abstract: Optical information and topographic information of the surface of a sample are measured at a nanometer-order resolution and with high reproducibility without damaging a probe and the sample by combining a nanometer-order cylindrical structure with a nanometer-order microstructure to form a plasmon intensifying near-field probe having a nanometer-order optical resolution and by repeating approach/retreat of the probe to/from each measurement point on the sample at a low contact force.

Abstract translation: 以纳米级分辨率和高重现性测量样品表面的光学信息和地形信息，而不损害探针和样品，通过将纳米级圆柱结构与纳米级微结构组合以形成等离子体激元附近 具有纳米级光学分辨率并且以低接触力重复将样品上的每个测量点的探针接近/退回。

公开(公告)号：US08610993B2

公开(公告)日：2013-12-17

申请号：US13141556

申请日：2009-12-24

Applicant: Naoya Matsumoto ,  Taro Ando ,  Takashi Inoue ,  Yoshiyuki Ohtake

Inventor： Naoya Matsumoto ,  Taro Ando ,  Takashi Inoue ,  Yoshiyuki Ohtake

IPC: G02F1/01 ,  G02F1/03

CPC classification number: G02B26/0808 ,  G02B21/086 ,  G02B26/06 ,  G02B27/4205 ,  G03H1/0841 ,  G03H2001/085 ,  G03H2225/32 ,  G03H2240/61

Abstract: A light control device 1 includes a light source 10, a prism 20, a spatial light modulator 30, a drive unit 31, a control unit 32, a lens 41, an aperture 42, and a lens 43. The spatial light modulator 30 is a phase modulating spatial light modulator, includes a plurality of two-dimensionally arrayed pixels, is capable of phase modulation in each of these pixels in a range of 4π, and presents a phase pattern to modulate the phase of light in each of the pixels. This phase pattern is produced by superimposing a blazed grating pattern for light diffraction with a phase modulation range of 2π or less and a phase pattern having a predetermined phase modulation distribution with a phase modulation range of 2π or less.

Abstract translation: 光控制装置1包括光源10，棱镜20，空间光调制器30，驱动单元31，控制单元32，透镜41，孔42和透镜43.空间光调制器30是 包括多个二维排列的像素的相位调制空间光调制器能够在4pi的范围内在这些像素的每一个中进行相位调制，并且呈现相位图案以调制每个像素中的光的相位。 该相位图案通过将相位调制范围为2pi以下的光衍射的闪耀光栅图案和相位调制范围为2pi以下的相位图案叠加而产生。

公开(公告)号：US08553733B2

公开(公告)日：2013-10-08

申请号：US12527618

申请日：2008-02-21

Applicant: Taro Ando ,  Yoshiyuki Ohtake ,  Naoya Matsumoto ,  Takashi Inoue ,  Haruyoshi Toyoda ,  Norihiro Fukuchi

Inventor： Taro Ando ,  Yoshiyuki Ohtake ,  Naoya Matsumoto ,  Takashi Inoue ,  Haruyoshi Toyoda ,  Norihiro Fukuchi

IPC: H01S3/10

CPC classification number: G01J1/08 ,  B23K26/03 ,  B23K26/066 ,  G01J1/02 ,  G01J1/0204 ,  G01J1/04 ,  G01J1/0414 ,  G01N21/8806 ,  G02B27/58 ,  G11B7/1367 ,  G11B7/1387

Abstract: A light source device 1 includes a laser light source 10 and an optical phase modulator 15 or the like. The optical phase modulator 15 inputs coherent light output from the laser light source 10 and transmitted through a beam splitter 14, phase-modulates the light according to the position on a beam cross section of the light, and outputs the phase-modulated light to the beam splitter 14. When (p+1) areas sectioned by p circumferences centered on a predetermined position are set on a beam cross section of light input to the optical phase modulator 15, the more outside each of the (p+1) areas is, the wider the radial width of the area, the amount of phase modulation is constant in each of the (p+1) areas, and the amounts of phase modulation differ by π between two adjacent areas out of the (p+1) areas.

Abstract translation: 光源装置1包括激光光源10和光相位调制器15等。 光相位调制器15输入从激光光源10输出的相干光，并透过分束器14，根据光束横截面上的位置对光进行相位调制，并将相位调制光输出到 当在输入到光相位调制器15的光束的横截面上设定以预定位置为中心的以p周为中心的（p + 1）区域时，每个（p + 1）区域越多 ，区域的径向宽度越宽，相位调制量在（p + 1）区域的每个区域中是恒定的，并且相位调制量在（p + 1）区域之间的两个相邻区域之间不同pi 。

公开(公告)号：US08466495B2

公开(公告)日：2013-06-18

申请号：US13468373

申请日：2012-05-10

Applicant: Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Yasuhiro Murase ,  Kazuki Ota ,  Akio Wakejima ,  Naotaka Kuroda

Inventor： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Yasuhiro Murase ,  Kazuki Ota ,  Akio Wakejima ,  Naotaka Kuroda

IPC: H01L29/80

CPC classification number: H01L29/7787 ,  H01L29/2003

Abstract: Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0≦y≦1); a carrier supply layer 13 composed of AlxGa1-xN (0≦x≦1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x

Abstract translation: 公开了一种HJFET 110，其包括：由In y Ga 1-y N（0 @ y 1）组成的沟道层12; 由Al x Ga 1-x N（0 @ x 1）构成的载流子供给层13，载流子供给层13设置在沟道层12上并且包括至少一个p型层; 以及源极电极15S，漏极电极15D和栅极电极17，其通过p型层面对沟道层12，并且设置在载流子供给层13上。满足以下关系式：5.6×10×11× NA×eta×t [cm-2] <5.6×1013x，其中x表示载体供给层的Al组成比，t表示所述p型层的厚度，NA表示杂质浓度，eta表示活化 比。

公开(公告)号：US08426895B2

公开(公告)日：2013-04-23

申请号：US12735817

申请日：2009-03-23

Applicant: Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando

Inventor： Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando

IPC: H01L29/205

CPC classification number: H01L29/7813 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/66734

Abstract: A semiconductor device capable of suppressing the occurrence of a punch-through phenomenon is provided. A first n-type conductive layer (2′) is formed on a substrate (1′). A p-type conductive layer (3′) is formed thereon. A second n-type conductive layer (4′) is formed thereon. On the under surface of the substrate (1′), there is a drain electrode (13′) connected to the first n-type conductive layer (2′). On the upper surface of the substrate (1′), there is a source electrode (11′) in ohmic contact with the second n-type conductive layer (4′), and a gate electrode (12′) in contact with the first n-type conductive layer (2′), p-type conductive layer (3′), the second n-type conductive layer (4′) through an insulation film (21′). The gate electrode (12′) and the source electrode (11′) are alternately arranged. The p-type conductive layer (3′) includes In.

Abstract translation: 提供能够抑制穿通现象发生的半导体器件。 在基板（1'）上形成第一n型导电层（2'）。 在其上形成p型导电层（3'）。 在其上形成第二n型导电层（4'）。 在基板（1'）的下表面上，连接有第一n型导电层（2'）的漏电极（13'）。 在基板（1'）的上表面上存在与第二n型导电层（4'）欧姆接触的源电极（11'）和与第一n型导电层（4'）接触的栅电极（12'） n型导电层（2'），p型导电层（3'），通过绝缘膜（21'）的第二n型导电层（4'）。 栅电极（12'）和源电极（11'）交替排列。 p型导电层（3'）包括In。

公开(公告)号：US20130069270A1

公开(公告)日：2013-03-21

申请号：US13698908

申请日：2010-05-24

Applicant: Itaru Sotome ,  Seiichiro Isobe ,  Takao Katagiri ,  Takashi Inoue ,  Hironobu Mano ,  Joju Niida ,  Hirokazu Takeuchi ,  TAkeshi Itou ,  Yuichiro Mizoguchi

Inventor： Itaru Sotome ,  Seiichiro Isobe ,  Takao Katagiri ,  Takashi Inoue ,  Hironobu Mano ,  Joju Niida ,  Hirokazu Takeuchi ,  TAkeshi Itou ,  Yuichiro Mizoguchi

IPC: B29B9/02

CPC classification number: B29B9/02 ,  B01J2/02 ,  B01J2/10 ,  B01J2/16

Abstract: A granulating method is a method in which powder containing a water-soluble component is granulated. In the disclosed granulating method, a dispersion element, wherein fine water droplets are dispersed in superheated steam, is expelled from a nozzle, and thus the dispersion element and powder in a flowing state come into contact with one another. It is preferable that the mass ratio of superheated steam contained in the dispersion element, as a mass ratio found from the theoretical flow amount of superheated steam expelled from the nozzle, and the actual flow amount of water supplied to the nozzle, be set in a range of 20-70 mass %.

Abstract translation: 造粒方法是将含有水溶性成分的粉末造粒的方法。 在公开的制粒方法中，将细水分散在过热蒸汽中的分散元件从喷嘴排出，因此分散元件和流动状态的粉末彼此接触。 优选的是，分散元件中所含的过热蒸汽的质量比，从从喷嘴排出的过热蒸汽的理论流量得到的质量比和供给到喷嘴的水的实际流量设定为 范围20-70质量％。