公开(公告)号：US20160372571A1

公开(公告)日：2016-12-22

申请号：US14902302

申请日：2014-09-02

Applicant: CSMC TECHNOLOGIES FAB1 CO.,LTD.

Inventor： Wanli Wang ,  Xiaoshe DENG ,  Genyi WANG ,  Qiang RUI

IPC: H01L29/66 ,  H01L21/308 ,  H01L29/06 ,  H01L21/265 ,  H01L29/739 ,  H01L21/268

CPC classification number: H01L29/66333 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/308 ,  H01L21/3247 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/41716 ,  H01L29/7395

Abstract: A reverse conducting insulated gate bipolar transistor (IGBT) manufacturing method, comprising the following steps: providing a substrate having an IGBT structure formed on the front surface thereof; implanting P+ ions onto the back surface of the substrate; forming a channel on the back surface of the substrate through photolithography and etching processes; planarizing the back surface of the substrate through a laser scanning process to form P-type and N-type interval structures; and forming a back surface collector by conducting a back metalizing process on the back surface of the substrate. Laser scanning process can process only the back surface structure requiring annealing, thus solve the problem of the front surface structure of the reverse conducting IGBT restricting back surface annealing to a low temperature, improving the P-type and N-type impurity activation efficiency in the back surface structure of the reverse conducting IGBT, and enhancing the performance of the reverse conducting IGBT.

Abstract translation: 一种反向导通绝缘栅双极晶体管（IGBT）制造方法，包括以下步骤：提供在其前表面上形成有IGBT结构的基板; 将P +离子注入衬底的背面; 通过光刻和蚀刻工艺在衬底的背表面上形成通道; 通过激光扫描工艺平坦化衬底的背面以形成P型和N型间隔结构; 以及通过在所述基板的背面进行背面金属化处理而形成背面集电体。 激光扫描过程只能处理需要退火的背面结构，从而解决了限制背面退火至低温的反向导通IGBT的前表面结构的问题，提高了P型和N型杂质的活化效率 反向导通IGBT的背面结构，提高反向导通IGBT的性能。

公开(公告)号：US09502534B2

公开(公告)日：2016-11-22

申请号：US14902294

申请日：2014-09-12

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shengrong Zhong ,  Genyi Wang ,  Xiaoshe Deng ,  Dongfei Zhou

IPC: H01L29/00 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L21/311 ,  H01L21/28 ,  H01L21/266 ,  H01L21/027 ,  H01L21/265 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/768 ,  H01L29/167

CPC classification number: H01L29/66666 ,  H01L21/02576 ,  H01L21/0273 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28035 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/768 ,  H01L29/0619 ,  H01L29/167 ,  H01L29/6609 ,  H01L29/66712 ,  H01L29/861

Abstract: A preparation method for a power diode, comprising: providing a substrate (10), the substrate (10) having a front surface and a back surface opposite to the front surface, an N-type layer (20) growing on the front surface of the substrate (10), and the N-type layer (20) having a first surface deviating from the substrate (10); forming a terminal protection ring (31, 32, 33); forming an oxide layer (50), and performing knot pushing on the terminal protection ring (31, 32, 33); conducting photoetching using a photoetching plate of an active region and etching the oxidation layer (50) of the active region, and forming a gate oxide layer (60) on the first surface of the N-type layer (20) of the active region; depositing on the gate oxide layer (60) to form a polysilicon layer (70); conducting photoetching using a polysilicon photoetching plate, taking a photoresist (40) as a mask layer to inject P-type ions into the N-type layer (20), and forming a P-type body region (82) beneath the polysilicon layer (70) through ion scattering; forming an N-type heavily doped region; forming a P+region; conducting thermal annealing, activating injected impurities and removing the photoresist (40); and conducting metallization processing on the first surface and the back surface of the substrate (10).

Abstract translation: 一种用于功率二极管的制备方法，包括：提供基板（10），所述基板（10）具有前表面和与所述前表面相对的后表面的N型层（20），所述N型层（20）在 所述基板（10）和具有偏离所述基板（10）的第一表面的所述N型层（20）。 形成端子保护环（31,32,33）; 形成氧化物层（50），并且对所述端子保护环（31,32,33）施加结压力; 使用有源区的光刻板进行光蚀刻，蚀刻有源区的氧化层（50），在有源区的N型层（20）的第一面上形成栅极氧化层（60） 沉积在栅极氧化物层（60）上以形成多晶硅层（70）; 使用多晶硅光刻板进行光蚀刻，以光致抗蚀剂（40）作为掩模层将P型离子注入到N型层（20）中，并在多晶硅层下形成P型体区（82） 70）通过离子散射; 形成N型重掺杂区域; 形成P +区; 进行热退火，激活注入的杂质和去除光致抗蚀剂（40）; 以及在所述基板（10）的所述第一表面和所述背面上进行金属化处理。

公开(公告)号：US09502497B2

公开(公告)日：2016-11-22

申请号：US14902270

申请日：2014-10-22

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Genyi Wang ,  Xiaoshe Deng ,  Shengrong Zong ,  Dongfei Zhou

IPC: H01L29/00 ,  H01L29/06 ,  H01L29/66 ,  H01L21/266 ,  H01L21/265 ,  H01L21/311 ,  H01L21/324 ,  H01L21/027 ,  H01L29/10 ,  H01L21/321 ,  H01L21/3213

CPC classification number: H01L29/0619 ,  H01L21/0273 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/31116 ,  H01L21/32105 ,  H01L21/32137 ,  H01L21/324 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/6606 ,  H01L29/66136 ,  H01L29/66204 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7811 ,  H01L29/8611

Abstract: A method for preparing a power diode, including: providing a substrate (10), growing a N type layer (20) on the front surface of the substrate (10); forming a terminal protecting ring; forming an oxide layer (30), knot-pushing to the terminal protecting ring; forming a gate oxide layer (60), depositing a poly-silicon layer (70) on the gate oxide layer (60); depositing a SiO2 layer (80) on the surface of the poly-silicon layer (70) and a oxide layer (50); forming a N type heavy doped region (92); forming a P+ region; removing a photoresist, implanting P type ions using the SiO2 layer (80) as a mask layer, and forming a P type body region; heat annealing; forming a side wall structure in the opening of the poly-silicon layer (70), the gate oxide layer (60) being etched, and removing the SiO2 layer (80); and processing a front surface metallization and a back surface metallization treatment. According to the method for preparing the power diode, by adjusting the isotropy etching level of the SiO2 layer and the ion implanting dose and energy, the threshold voltage of a DMOS structure can be adjusted, and the adjustment of the forward voltage drop for the device can be achieved.

Abstract translation: 一种制备功率二极管的方法，包括：提供衬底（10），在衬底（10）的前表面上生长N型层（20）; 形成端保护环; 形成氧化物层（30），向所述端子保护环打结; 形成栅极氧化物层（60），在所述栅极氧化物层（60）上沉积多晶硅层（70）。 在所述多晶硅层（70）的表面和氧化物层（50）上沉积SiO 2层（80）; 形成N型重掺杂区域（92）; 形成P +区; 去除光致抗蚀剂，使用SiO 2层（80）作为掩模层注入P型离子，形成P型体区; 热退火; 在所述多晶硅层（70）的开口部形成侧壁结构，蚀刻所述栅极氧化物层（60），除去所述SiO 2层（80）。 以及处理前表面金属化和背面金属化处理。 根据制备功率二极管的方法，通过调整SiO2层的各向同性蚀刻水平和离子注入剂量和能量，可以调整DMOS结构的阈值电压，并调整器件的正向压降 可以实现。

公开(公告)号：US20160308029A1

公开(公告)日：2016-10-20

申请号：US14902294

申请日：2014-09-12

Applicant: CSMC Technologies Fab1 Co., Ltd.

Inventor： Shengrong Zhong ,  Genyi Wang ,  Xiaoshe Deng ,  Dongfei Zhou

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/311 ,  H01L21/28 ,  H01L29/167 ,  H01L21/027 ,  H01L21/265 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/768 ,  H01L21/02 ,  H01L21/266

CPC classification number: H01L29/66666 ,  H01L21/02576 ,  H01L21/0273 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28035 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/768 ,  H01L29/0619 ,  H01L29/167 ,  H01L29/6609 ,  H01L29/66712 ,  H01L29/861

Abstract: A preparation method for a power diode, comprising: providing a substrate (10), the substrate (10) having a front surface and a back surface opposite to the front surface, an N-type layer (20) growing on the front surface of the substrate (10), and the N-type layer (20) having a first surface deviating from the substrate (10); forming a terminal protection ring (31, 32, 33); forming an oxide layer (50), and performing knot pushing on the terminal protection ring (31, 32, 33); conducting photoetching using a photoetching plate of an active region and etching the oxidation layer (50) of the active region, and forming a gate oxide layer (60) on the first surface of the N-type layer (20) of the active region; depositing on the gate oxide layer (60) to form a polysilicon layer (70); conducting photoetching using a polysilicon photoetching plate, taking a photoresist (40) as a mask layer to inject P-type ions into the N-type layer (20), and forming a P-type body region (82) beneath the polysilicon layer (70) through ion scattering; forming an N-type heavily doped region; forming a P+region; conducting thermal annealing, activating injected impurities and removing the photoresist (40); and conducting metallization processing on the first surface and the back surface of the substrate (10).

Abstract translation: 一种用于功率二极管的制备方法，包括：提供基板（10），所述基板（10）具有前表面和与所述前表面相对的后表面的N型层（20），所述N型层（20）在 所述基板（10）和具有偏离所述基板（10）的第一表面的所述N型层（20）。 形成端子保护环（31,32,33）; 形成氧化物层（50），并且对所述端子保护环（31,32,33）施加结压力; 使用有源区的光刻板进行光蚀刻，蚀刻有源区的氧化层（50），在有源区的N型层（20）的第一面上形成栅极氧化层（60） 沉积在栅极氧化物层（60）上以形成多晶硅层（70）; 使用多晶硅光刻板进行光蚀刻，以光致抗蚀剂（40）作为掩模层将P型离子注入到N型层（20）中，并在多晶硅层下形成P型体区（82） 70）通过离子散射; 形成N型重掺杂区域; 形成P +区; 进行热退火，激活注入的杂质和去除光致抗蚀剂（40）; 以及在所述基板（10）的所述第一表面和所述背面上进行金属化处理。

公开(公告)号：US20160240608A1

公开(公告)日：2016-08-18

申请号：US14901606

申请日：2014-06-06

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shuo ZHANG ,  Qiang RUI ,  Xiaoshe DENG ,  Genyi WANG

IPC: H01L29/06 ,  H01L23/31 ,  H01L23/528 ,  H01L23/532 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/0607 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/528 ,  H01L23/53219 ,  H01L23/53247 ,  H01L29/0619 ,  H01L29/0834 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/7393 ,  H01L29/7395

Abstract: A field-stop reverse conducting insulated gate bipolar transistor and a manufacturing method thereof. The transistor comprises a terminal structure (200) and an active region (100). An underlayment of the field-stop reverse conducting insulated gate bipolar transistor is an N-type underlayment, the back surface of the underlayment is provided with an N-type electric field stop layer (1), one surface of the electric field stop layer (1) departing from the underlayment is provided with a back-surface P-type structure (10), and the surface of the back-surface P-type structure (10) is provided with a back-surface metal layer (12). A plurality of polysilicon filling structures (11) which penetrate into the electric field stop layer (1) from the back-surface P-type structure (10) are formed in the active region (100).

Abstract translation: 场阻反向导通绝缘栅双极晶体管及其制造方法。 晶体管包括端子结构（200）和有源区（100）。 场阻反向导通绝缘栅双极晶体管的底层是N型衬垫，衬垫的背面设置有N型电场停止层（1），电场停止层的一个表面 在背衬P型结构（10）的背面设置有背面金属层（12）的背面P型结构（10）的表面。 在有源区（100）中形成有从背面P型结构（10）贯穿电场停止层（1）的多个多晶硅填充结构（11）。

公开(公告)号：US20160232980A1

公开(公告)日：2016-08-11

申请号：US15025846

申请日：2014-10-10

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shuming GUO ,  Guoyi ZONG

IPC: G11C16/26 ,  G11C16/32 ,  G11C16/24

CPC classification number: G11C16/26 ,  G11C16/24 ,  G11C16/32

Abstract: A readout circuit with a self-detection circuit and a control method therefor. The circuit comprises a pre-charging circuit and a control circuit, the pre-charging circuit and the control circuit being connected to a first node and used for charging a memory unit. The readout circuit also comprises a detection circuit, the detection circuit and the pre-charging circuit being connected to the first node. The detection circuit comprises a third NOT gate, a fourth NOT gate, a first NAND gate, a sixth NOT gate, a first trigger and an eighth NOT gate. In such a manner of detecting the reversal of the first NOT gate through the reversal of the third NOT gate, the charging duration of the first node (A) can be greatly reduced, thereby reducing the reading duration of the whole circuit. At the same time, the re-occurrence of a state of charging the circuit can be avoided after pre-charging has ended.

Abstract translation: 一种具有自检电路及其控制方法的读出电路。 该电路包括预充电电路和控制电路，预充电电路和控制电路连接到第一节点并用于对存储器单元充电。 读出电路还包括检测电路，检测电路和预充电电路连接到第一节点。 检测电路包括第三NOT门，第四NOT门，第一NAND门，第六NOT门，第一触发器和第八NOT门。 以这样的方式，通过第三非门的反相来检测第一非门的反向，可以大大减少第一节点（A）的充电持续时间，从而减少整个电路的读取持续时间。 同时，在预充电结束之后可以避免电路充电状态的再次发生。

公开(公告)号：US09397106B2

公开(公告)日：2016-07-19

申请号：US14398753

申请日：2013-05-09

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shuming Guo

IPC: G06F17/50 ,  H01L27/115 ,  H01L27/02 ,  G11C17/12 ,  H01L27/112

CPC classification number: H01L27/115 ,  G06F17/5068 ,  G11C17/12 ,  H01L27/0207 ,  H01L27/11233

Abstract: A method of producing a Macro Read Only Memory (MROM) memory based on a One Time Programmable (OTP) memory is provided. The method includes: removing a floating gate of a second P-type Metal Oxide Semiconductor (PMOS) transistor of an OTP memory cell for storing data “0” in an OTP memory map, such that the OTP memory cell being transferred to a MROM memory cell for storing data “0”, and retaining an original structure of the OTP memory cell for storing data “1” in the OTP memory map, such that the original structure being used as a MROM memory cell for storing data “1”, thus forming a MROM memory map; and producing a MROM memory according to a MROM memory map. The OTP memory map is debugged to determine data which can be changed into the MROM memory map, and an OTP process can be transferred into a MROM process by adjusting only one mask during a producing process.

Abstract translation: 提供了一种基于一次可编程（OTP）存储器产生宏存储器（MROM）存储器的方法。 该方法包括：移除OTP存储单元的第二P型金属氧化物半导体（PMOS）晶体管的浮置栅极，用于将数据“0”存储在OTP存储器映射中，使得OTP存储器单元被传送到MROM存储器 用于存储数据“0”的单元，并将用于存储数据“1”的OTP存储单元的原始结构保留在OTP存储器映射中，使得原始结构用作用于存储数据“1”的MROM存储单元，因此 形成MROM记忆图; 并根据MROM存储器映射产生MROM存储器。 调试OTP存储器映射以确定可以改变为MROM存储器映射的数据，并且可以通过在生产过程中仅调整一个掩模将OTP处理传送到MROM过程。

公开(公告)号：US20160163841A1

公开(公告)日：2016-06-09

申请号：US14392251

申请日：2014-06-05

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shuo ZHANG ,  Qiang RUI ,  Genyi WANG ,  Xiaoshe DENG

IPC: H01L29/739 ,  H01L29/08 ,  H01L29/66 ,  H01L29/49 ,  H01L21/02 ,  H01L29/417 ,  H01L21/311 ,  H01L21/265 ,  H01L21/324 ,  H01L29/423 ,  H01L21/285 ,  H01L29/40 ,  H01L21/28

CPC classification number: H01L29/7395 ,  H01L21/02164 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/2855 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/0619 ,  H01L29/0804 ,  H01L29/0834 ,  H01L29/402 ,  H01L29/404 ,  H01L29/405 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/66333

Abstract: A field-stop reverse conducting insulated gate bipolar transistor and a manufacturing method therefor. The transistor comprises a terminal structure (200) and an active region (100). An underlayment of the field-stop reverse conducting insulated gate bipolar transistor is an N-type underlayment, the back surface of the underlayment is provided with an N-type electric field stop layer (1), one surface of the electric field stop layer departing from the underlayment is provided with a back-surface P-type structure (10), and the surface of the back-surface P-type structure is provided with a back-surface metal layer (12). A plurality of notches (11) which penetrate through the back-surface P-type structure (10) from the back-surface metal layer (12) to the electric field stop layer (1) are formed in the active region (100), and metals of the back-surface metal layer (12) are filled into the notches (11) to form a metal structure which extends into the electric field stop layer (1).

Abstract translation: 一种场控反向导通绝缘栅双极晶体管及其制造方法。 晶体管包括端子结构（200）和有源区（100）。 场阻反向导通绝缘栅双极晶体管的底层是N型垫层，底层的背面设置有N型电场停止层（1），电场停止层的一个表面离开 从垫层设置有背面P型结构（10），并且背面P型结构的表面设置有背面金属层（12）。 在有源区域（100）中形成有从后表面金属层（12）穿过背面P型结构（10）到电场停止层（1）的多个凹口（11） 并且背面金属层（12）的金属填充到凹口（11）中以形成延伸到电场停止层（1）中的金属结构。

公开(公告)号：US20150333176A1

公开(公告)日：2015-11-19

申请号：US14651706

申请日：2013-12-31

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Zheng Bian

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L21/265 ,  H01L29/40

CPC classification number: H01L29/7813 ,  H01L21/265 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/4916 ,  H01L29/66681 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

Abstract: A trench-type DMOS device and a manufacturing method thereof are provided. The DMOS device includes: a substrate (100) used as a public drain region, an active region (102) and a voltage-dividing ring (103) formed on the substrate (100), and a first dielectric layer (110) formed on the substrate (100). Multiple trenches are located on the first dielectric layer (110), and the trenches extend from the surface of the first dielectric layer (110) into the interior of the substrate (100). The trenches comprise at least one first trench (141) distributed in the active region (102) and a second trench (142) outside the active region (102). A gate oxide layer (144) is formed in the trench and polycrystalline silicon (143) is filled to form a gate. The active region (102) further comprises a source electrode region (104) and a P-type heavily doped region (105) under the source electrode region (104). A second dielectric layer (120) covers the first dielectric layer (110) and the multiple trenches. A metal layer (130) covers the second dielectric layer (120) to form a first electrode region (131) and a second electrode region (132). By increasing the cross-sectional area of the polycrystalline silicon (143) in the gate, the resistance of the gate is reduced.

Abstract translation: 提供沟槽式DMOS器件及其制造方法。 DMOS装置包括：用作公共漏极区域的基板（100），形成在基板（100）上的有源区域（102）和分压环（103）;以及第一介电层（110），形成在 基板（100）。 多个沟槽位于第一介电层（110）上，并且沟槽从第一介电层（110）的表面延伸到衬底（100）的内部。 沟槽包括分布在有源区域（102）中的至少一个第一沟槽（141）和在有源区域（102）之外的第二沟槽（142）。 在沟槽中形成栅极氧化层（144），填充多晶硅（143）以形成栅极。 有源区（102）还包括在源电极区（104）下面的源电极区（104）和P型重掺杂区（105）。 第二电介质层（120）覆盖第一电介质层（110）和多个沟槽。 金属层（130）覆盖第二电介质层（120）以形成第一电极区域（131）和第二电极区域（132）。 通过增加栅极中的多晶硅（143）的横截面积，栅极的电阻降低。

公开(公告)号：US20150143320A1

公开(公告)日：2015-05-21

申请号：US14398753

申请日：2013-05-09

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shuming Guo

IPC: H01L27/115 ,  G06F17/50 ,  H01L27/02

CPC classification number: H01L27/115 ,  G06F17/5068 ,  G11C17/12 ,  H01L27/0207 ,  H01L27/11233

Abstract: A method of producing a MROM memory based on an OTP memory is provided. The method includes: removing the floating gate of the second PMOS transistor of the OTP memory cell for storing data “0” in the OTP memory map, such that the OTP memory cell being transferred to a MROM memory cell for storing data “0”, and retaining the original structure of the OTP memory cell for storing data “1” in the OTP memory map, such that the original structure being used as a MROM memory cell for storing data “1”, thus forming a MROM memory map; and producing a MROM memory according to the MROM memory map. According to the present invention, the OTP memory map which is debugged and has determined data can be changed into the MROM memory map, and the OTP process can be transferred into the MROM process by adjusting only one mask during the producing process. The present invention greatly saves the time and cost of the device programming and testing, thus simplifying the process and saving the cost, increasing the profit.

Abstract translation: 提供了一种基于OTP存储器生成MROM存储器的方法。 该方法包括：移除OTP存储器单元中的第二PMOS晶体管的浮置栅极用于在OTP存储器映射中存储数据“0”，使得OTP存储器单元被传送到用于存储数据“0”的MROM存储单元， 并且将OTP存储单元的原始结构保留在OTP存储器映射中，使得原始结构被用作用于存储数据“1”的MROM存储单元，从而形成MROM存储器映射; 并根据MROM存储器映射产生MROM存储器。 根据本发明，调试并确定了数据的OTP存储器映射可以改变为MROM存储器映射，并且可以通过在生产过程中仅调整一个掩码来将OTP处理传送到MROM处理。 本发明大大节省了设备编程和测试的时间和成本，从而简化了流程并节省了成本，增加了利润。