公开(公告)号：US09401422B2

公开(公告)日：2016-07-26

申请号：US14651706

申请日：2013-12-31

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Zheng Bian

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L21/265 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/4916 ,  H01L29/66681 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

Abstract: A trench-type DMOS device includes a substrate as a public drain region, an active region and a voltage-dividing ring formed on the substrate, and a first dielectric layer formed on the substrate. Multiple trenches are located on the first dielectric layer, and the trenches extend from the surface of the first dielectric layer into the interior of the substrate. The trenches comprise at least one first trench distributed in the active region and a second trench outside the active region. A gate oxide layer is formed in the trench and polycrystalline silicon is filled to form a gate. The active region further comprises a source electrode region and a P-type heavily doped region under the source electrode region. A second dielectric layer covers the first dielectric layer and the multiple trenches. A metal layer covers the second dielectric layer to form a first electrode region and a second electrode region.

Abstract translation: 沟槽型DMOS器件包括作为公共漏极区域的衬底，形成在衬底上的有源区和分压环，以及形成在衬底上的第一电介质层。 多个沟槽位于第一电介质层上，并且沟槽从第一电介质层的表面延伸到衬底的内部。 沟槽包括分布在有源区中的至少一个第一沟槽和在有源区之外的第二沟槽。 在沟槽中形成栅极氧化层，填充多晶硅以形成栅极。 有源区还包括在源电极区下面的源电极区和P型重掺杂区。 第二电介质层覆盖第一电介质层和多个沟槽。 金属层覆盖第二电介质层以形成第一电极区域和第二电极区域。

公开(公告)号：US20150333176A1

公开(公告)日：2015-11-19

申请号：US14651706

申请日：2013-12-31

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Zheng Bian

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L21/265 ,  H01L29/40

CPC classification number: H01L29/7813 ,  H01L21/265 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/4916 ,  H01L29/66681 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

Abstract: A trench-type DMOS device and a manufacturing method thereof are provided. The DMOS device includes: a substrate (100) used as a public drain region, an active region (102) and a voltage-dividing ring (103) formed on the substrate (100), and a first dielectric layer (110) formed on the substrate (100). Multiple trenches are located on the first dielectric layer (110), and the trenches extend from the surface of the first dielectric layer (110) into the interior of the substrate (100). The trenches comprise at least one first trench (141) distributed in the active region (102) and a second trench (142) outside the active region (102). A gate oxide layer (144) is formed in the trench and polycrystalline silicon (143) is filled to form a gate. The active region (102) further comprises a source electrode region (104) and a P-type heavily doped region (105) under the source electrode region (104). A second dielectric layer (120) covers the first dielectric layer (110) and the multiple trenches. A metal layer (130) covers the second dielectric layer (120) to form a first electrode region (131) and a second electrode region (132). By increasing the cross-sectional area of the polycrystalline silicon (143) in the gate, the resistance of the gate is reduced.

Abstract translation: 提供沟槽式DMOS器件及其制造方法。 DMOS装置包括：用作公共漏极区域的基板（100），形成在基板（100）上的有源区域（102）和分压环（103）;以及第一介电层（110），形成在 基板（100）。 多个沟槽位于第一介电层（110）上，并且沟槽从第一介电层（110）的表面延伸到衬底（100）的内部。 沟槽包括分布在有源区域（102）中的至少一个第一沟槽（141）和在有源区域（102）之外的第二沟槽（142）。 在沟槽中形成栅极氧化层（144），填充多晶硅（143）以形成栅极。 有源区（102）还包括在源电极区（104）下面的源电极区（104）和P型重掺杂区（105）。 第二电介质层（120）覆盖第一电介质层（110）和多个沟槽。 金属层（130）覆盖第二电介质层（120）以形成第一电极区域（131）和第二电极区域（132）。 通过增加栅极中的多晶硅（143）的横截面积，栅极的电阻降低。