公开(公告)号：US10983833B2

公开(公告)日：2021-04-20

申请号：US16527441

申请日：2019-07-31

Applicant: International Business Machines Corporation

Inventor： Brenton F. Belmar ,  Christian Jacobi ,  Matthias Klein ,  Peter G. Sutton

IPC: G06F9/50

Abstract: An aspect includes hardware accelerator access. An application executing on a core of a multi-core processor triggers an interface code routine to acquire ownership of a hardware accelerator that is shared by a plurality of cores. The interface code routine partitions an input work package of the application into a plurality of pages in one or more input queues. The input work package is provided to the hardware accelerator in groups of one or more pages through the one or more input queues based on acquiring ownership of the hardware accelerator.

公开(公告)号：US10949097B2

公开(公告)日：2021-03-16

申请号：US16682481

申请日：2019-11-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Edward W. Chencinski ,  Bruce Ratcliff ,  Eric N. Lais ,  Michael James Becht ,  Matthias Klein

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42

Abstract: A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.

公开(公告)号：US20210064440A1

公开(公告)日：2021-03-04

申请号：US16550829

申请日：2019-08-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Matthias Klein ,  Timothy Slegel ,  Anthony T. Sofia ,  Simon Weishaupt ,  Bruce C. Giamei ,  Louis P. Gomes ,  Mahmoud Amin

IPC: G06F9/50 ,  G06F9/52 ,  H03M7/30

Abstract: A processor requests that a data transformation operation be performed using another processor, in which the data transformation operation is performed asynchronously. A determination is made that the data transformation operation performed using the other processor has completed unsatisfactorily, and based on the unsatisfactory completion, status relating to performance of the data transformation operation is incomplete. The data transformation operation is then re-executed synchronously using the one processor, and the re-executing provides status information unavailable in performing the data transformation operation asynchronously.

公开(公告)号：US20210034438A1

公开(公告)日：2021-02-04

申请号：US16527424

申请日：2019-07-31

Applicant: International Business Machines Corporation

Inventor： Robert J. Sonnelitter, III ,  Michael Fee ,  Craig R. Walters ,  Arthur O'Neill ,  Matthias Klein

IPC: G06F9/52 ,  G06F9/48 ,  G06F9/38 ,  G06F9/54 ,  G06F12/0802

Abstract: Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data. In response to the memory address matching a memory address stored in the shared controller, the shared controller acknowledges the at least one intermediary controller's fetch request, wherein upon acknowledgement, the at least one intermediary controller resets. In response to release of the data by a second requesting agent, the shared controller transmits the data to the first requesting agent.

公开(公告)号：US10831497B2

公开(公告)日：2020-11-10

申请号：US16263786

申请日：2019-01-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce C. Giamei ,  Anthony T. Sofia ,  Matthias Klein ,  Simon Weishaupt ,  Mark S. Farrell ,  Timothy Slegel ,  Ashutosh Mishra ,  Christian Jacobi

IPC: G06F9/30 ,  H03M7/40 ,  G06F9/38 ,  G06F9/355

Abstract: An instruction to perform a function of a plurality of functions is obtained. The instruction is a single architected instruction of an instruction set architecture that complies to an industry standard for compression. The instruction is executed, and the executing includes performing the function specified by the instruction. The performing includes, based on the function being a compression function or a decompression function, transforming state of input data between an uncompressed form of the input data and a compressed form of the input data to provide a transformed state of data accessing. During performing the function, history relating to the function is accessed. The history is to be used in transforming the state of input data between the uncompressed form and the compressed form.

公开(公告)号：US20200295780A1

公开(公告)日：2020-09-17

申请号：US16353527

申请日：2019-03-14

Applicant: International Business Machines Corporation

Inventor： Timothy Slegel ,  Mark Farrell ,  Bruce Giamei ,  Matthias Klein ,  Ashutosh Misra ,  Simon Weishaupt ,  Girish Gopala Kurup

IPC: H03M13/01 ,  H03M7/40 ,  G06F9/50 ,  G06F7/58 ,  H03M13/00

Abstract: Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for verifying the correctness of the DEFLATE compression accelerator. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. A switch is communicatively coupled to the output of the input buffer and to the output of the LZ77 compressor. The switch is configured to bypass the LZ77 compressor during a compression test. The accelerator further includes a deflate Huffman encoder communicatively coupled to an output of the switch and an output buffer communicatively coupled to the deflate Huffman encoder. When the switch is not bypassed, the compressor can be modified to produce repeatable results.

公开(公告)号：US20200293377A1

公开(公告)日：2020-09-17

申请号：US16741974

申请日：2020-01-14

Applicant: International Business Machines Corporation

Inventor： Timothy Slegel ,  Mark Farrell ,  Bruce Giamei ,  Matthias Klein ,  Ashutosh Misra ,  Simon Weishaupt ,  Girish Gopala Kurup

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/38 ,  H03M7/40 ,  H03M7/30

Abstract: Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for verifying the correctness of the DEFLATE compression accelerator. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. A switch is communicatively coupled to the output of the input buffer and to the output of the LZ77 compressor. The switch is configured to bypass the LZ77 compressor during a compression test. The accelerator further includes a deflate Huffman encoder communicatively coupled to an output of the switch and an output buffer communicatively coupled to the deflate Huffman encoder. When the switch is not bypassed, the compressor can be modified to produce repeatable results.

公开(公告)号：US20200285592A1

公开(公告)日：2020-09-10

申请号：US16292762

申请日：2019-03-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ekaterina M. Ambroladze ,  Robert J. Sonnelitter, III ,  Matthias Klein ,  Craig Walters ,  Kevin Lopes ,  Michael A. Blake ,  Tim Bronson ,  Kenneth Klapproth ,  Vesselina Papazova ,  Hieu T Huynh

IPC: G06F12/126 ,  G06F12/0811 ,  G06F12/084

Abstract: Embodiments of the present invention are directed to a computer-implemented method for cache eviction. The method includes detecting a first data in a shared cache and a first cache in response to a request by a first processor. The first data is determined to have a mid-level cache eviction priority. A request is detected from a second processor for a same first data as requested by the first processor. However, in this instance, the second processor has indicated that the same first data has a low-level cache eviction priority. The first data is duplicated and loaded to a second cache, however, the data has a low-level cache eviction priority at the second cache.

公开(公告)号：US10756758B1

公开(公告)日：2020-08-25

申请号：US16556925

申请日：2019-08-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bulent Abali ,  Ashutosh Misra ,  Matthias Klein

IPC: H03M7/40 ,  H03M7/30 ,  G06F9/50

Abstract: Various embodiments are provided for length-limited Huffman encoding in a data compression accelerator in a computing environment by a processor. Symbol counts of a plurality of symbols in compressed data may be normalized and manipulated according to a maximum code length limiting operation such that those of the plurality of symbols having a least frequent symbol count have a symbol count equal to a maximum code length of a Huffman tree.

公开(公告)号：US20200264910A1

公开(公告)日：2020-08-20

申请号：US16789519

申请日：2020-02-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Marco Kraemer ,  Christoph Raisch ,  Bernd Nerz ,  Donald William Schmidt ,  Matthias Klein ,  Sascha Junghans ,  Peter Dana Driever

IPC: G06F9/455 ,  G06F9/48 ,  G06F9/50 ,  G06F9/54

Abstract: An interrupt signal is provided to a guest operating system. A bus connected module is operationally connected with a plurality of processors via a bus attachment device. The bus attachment device receives an interrupt signal from the bus connected module with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is running using a running indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor is running, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.