公开(公告)号：US12080628B2

公开(公告)日：2024-09-03

申请号：US18132801

申请日：2023-04-10

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Choong Kooi Chee ,  Jackson Chung Peng Kong ,  Wai Ling Lee ,  Tat Hin Tan

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/822 ,  H01L23/00 ,  H01L23/48 ,  H01L25/16 ,  H01L49/02

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L21/8221 ,  H01L24/09 ,  H01L24/17 ,  H01L25/16 ,  H01L28/40

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

公开(公告)号：US12002747B2

公开(公告)日：2024-06-04

申请号：US17680489

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jenny Shio Yin Ong ,  Seok Ling Lim ,  Kooi Chi Ooi ,  Jackson Chung Peng Kong

IPC: H01L23/50 ,  H01G4/12 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L25/065 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01G4/1272 ,  H01L23/5286 ,  H01L23/5381 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/0655 ,  H01L28/60

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device can include a semiconductor package including a package substrate, a first semiconductor die on the package substrate, a second semiconductor die on the package substrate, a third semiconductor die on the package substrate, and a bridge interconnect at least partially embedded in the package substrate. The bridge interconnect can include a first bridge section coupling the first semiconductor die to the second semiconductor die, a second bridge section coupling the second semiconductor die to the third semiconductor die, and a power-ground section between the first section and the second section, the power-ground section comprising first and second conductive traces coupled to the second semiconductor die.

公开(公告)号：US11942412B2

公开(公告)日：2024-03-26

申请号：US17069421

申请日：2020-10-13

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Min Suet Lim ,  Tin Poay Chuah

IPC: H01L23/498 ,  H01L23/538 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H05K3/46

CPC classification number: H01L23/4985 ,  H01L23/49816 ,  H01L23/5387 ,  H05K1/144 ,  H05K1/147 ,  H05K1/189 ,  H05K3/361 ,  H05K3/4697 ,  H05K2201/10378

Abstract: To address the issue of shrinking volume that can be allocated for electrical components, a system can use an interposer with a flexible portion. A first portion of the interposer can electrically connect to a top side of a motherboard. A flexible portion of the interposer, adjacent to the first portion, can wrap around an edge of the motherboard. A peripheral portion of the interposer, adjacent to the flexible portion, can electrically connect to a bottom side of the motherboard. The peripheral portion can be flexible or rigid. The interposer can define a cavity that extends through the first portion of the interposer. A chip package can electrically connect to the first portion of the interposer. The chip package can be coupled to at least one electrical component that extends into the cavity when the chip package is connected to the interposer.

公开(公告)号：US11837458B2

公开(公告)日：2023-12-05

申请号：US17498089

申请日：2021-10-11

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Ping Ping Ooi ,  Kooi Chi Ooi

IPC: H01L23/66 ,  H01L21/48 ,  H01L23/498 ,  H01L21/768 ,  H01L23/48 ,  H05K3/00 ,  H05K3/42

CPC classification number: H01L23/66 ,  H01L21/481 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49894 ,  H01L21/76898 ,  H01L23/481 ,  H01L2223/6616 ,  H05K3/0094 ,  H05K3/426

Abstract: An electronic circuit including a substrate having a first dielectric characteristic. The substrate can include a first side and a second side. An intermediary material can be disposed within the substrate. For instance, the intermediary material can be located between the first side and the second side. The intermediary material can include a second dielectric characteristic, where the second dielectric characteristic is different than the first dielectric characteristic. A first conductive layer can be disposed on the first side, and a second conductive layer can be disposed on the second side. A conductive path can be electrically coupled between the first conductive layer and the second conductive layer. The conductive path can be in contact with at least a portion of the intermediary material.

公开(公告)号：US11562954B2

公开(公告)日：2023-01-24

申请号：US16912619

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Seok Ling Lim ,  Jenny Shio Yin Ong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L29/00 ,  H01L29/76 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: Disclosed embodiments include frame-array interconnects that have a ledge portion to accommodate a passive device. A seated passive device is between at least two frame-array interconnects for semiconductor package-integrated decoupling capacitors.

公开(公告)号：US11527467B2

公开(公告)日：2022-12-13

申请号：US17089749

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Seok Ling Lim ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong ,  Kooi Chi Ooi

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/13 ,  H01L23/552

Abstract: According to the various aspects, a multi-chip semiconductor package includes a package substrate, an interconnect frame extending beyond a first side edge of the package substrate, the interconnect frame including a bottom surface positioned over and coupled to a top surface of the package substrate, a first semiconductor device positioned at least partially over and coupled to the interconnect frame, and a second semiconductor device positioned on the bottom surface of the interconnect frame alongside of the package substrate. The interconnect frame further includes a redistribution layer and a frame construct layer, and a plurality of vias coupled to the redistribution layer, with the frame construct layer further includes a recessed area, and the first semiconductor device is positioned in the recessed area.

公开(公告)号：US20220392835A1

公开(公告)日：2022-12-08

申请号：US17680489

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jenny Shio Yin Ong ,  Seok Ling Lim ,  Kooi Chi Ooi ,  Jackson Chung Peng Kong

IPC: H01L23/522 ,  H01L23/538 ,  H01L23/528 ,  H01L49/02 ,  H01G4/12 ,  H01L25/065

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device can include a semiconductor package including a package substrate, a first semiconductor die on the package substrate, a second semiconductor die on the package substrate, a third semiconductor die on the package substrate, and a bridge interconnect at least partially embedded in the package substrate. The bridge interconnect can include a first bridge section coupling the first semiconductor die to the second semiconductor die, a second bridge section coupling the second semiconductor die to the third semiconductor die, and a power-ground section between the first section and the second section, the power-ground section comprising first and second conductive traces coupled to the second semiconductor die.

公开(公告)号：US11462488B2

公开(公告)日：2022-10-04

申请号：US17090926

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong

IPC: H01L23/00 ,  H01L23/14 ,  H01L21/48 ,  H01L23/498 ,  H01L23/16

Abstract: According to the various aspects, a package substrate with a heterogeneous substrate core including a first core layer that is coextensive with the package substrate and extends through a first section and a second section of the substrate core, in which the first section is adjacent to and thicker than the second section. The first section having at least a second layer and/or a third layer to provide the difference in thickness with the second section.

公开(公告)号：US11430764B2

公开(公告)日：2022-08-30

申请号：US17024056

申请日：2020-09-17

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Seok Ling Lim ,  Jenny Shio Yin Ong ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/66

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a semiconductor article having a package substrate, a first semiconductor die coupled to the package substrate, a second semiconductor die coupled to the package substrate and adjacent the first semiconductor die, and a bridge component therebetween coupling the first semiconductor die to the second semiconductor die. The bridge component can include a bridge substrate, a conductive trace therein, and a passive component coupled to the conductive trace.

公开(公告)号：US11367673B2

公开(公告)日：2022-06-21

申请号：US17089750

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong

IPC: H01L23/49 ,  H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H01L23/48 ,  H01L25/16 ,  H01L23/00

Abstract: According to various examples, a device is described. The device may include an interposer. The device may also include a plurality of first through-silicon-vias disposed in the interposer, wherein the plurality of first through-silicon-vias have a first diameter. The device may also include a plurality of second through-silicon-vias disposed in the interposer, wherein the plurality of second through-silicon-vias have a second diameter larger than the first via diameter. The device may also include a first recess in the interposer positioned at bottom ends of the plurality of second through-silicon-vias.