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    Substrate with gradiated dielectric for reducing impedance mismatch
    3.
    发明授权
    Substrate with gradiated dielectric for reducing impedance mismatch 有权

    公开(公告)号：US11164827B2

    公开(公告)日：2021-11-02

    申请号：US16473962

    申请日：2017-12-19

    Applicant: Intel Corporation

    Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Ping Ping Ooi ,  Kooi Chi Ooi

    IPC: H01L23/66 ,  H01L21/48 ,  H01L23/498 ,  H01L21/768 ,  H01L23/48

    Abstract: An electronic circuit including a substrate having a first dielectric characteristic. The substrate can include a first side and a second side. An intermediary material can be disposed within the substrate. For instance, the intermediary material can be located between the first side and the second side. The intermediary material can include a second dielectric characteristic, where the second dielectric characteristic is different than the first dielectric characteristic. A first conductive layer can be disposed on the first side, and a second conductive layer can be disposed on the second side. A conductive path can be electrically coupled between the first conductive layer and the second conductive layer. The conductive path can be in contact with at least a portion of the intermediary material.

    STACKED DICE SYSTEMS
    4.
    发明申请
    STACKED DICE SYSTEMS 审中-公开

    公开(公告)号：US20200083194A1

    公开(公告)日：2020-03-12

    申请号：US16473570

    申请日：2017-11-29

    Applicant: Intel Corporation

    Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi ,  Ping Ping Ooi

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48

    Abstract: Discussed generally herein are devices that can include multiple stacked dice electrically coupled to dice electrically coupled to a peripheral sidewall of the stacked dice and/or a dice stack electrically coupled to a passive die. In one or more embodiments a device can include a dice stack comprising at least two dice including a first die and a second die, the first die electrically connected to and on a second die, a first side pad on, or at least partially in, a first sidewall of the dice stack, a third die electrically connected to the first die at a first surface of the third die and through the first side pad, and a fourth die electrically connected to the third die at a second surface of the first die, the second side opposite the first side.

    SUBSTRATE WITH GRADIATED DIELECTRIC FOR REDUCING IMPEDANCE MISMATCH
    6.
    发明申请
    SUBSTRATE WITH GRADIATED DIELECTRIC FOR REDUCING IMPEDANCE MISMATCH 有权

    公开(公告)号：US20220102295A1

    公开(公告)日：2022-03-31

    申请号：US17498089

    申请日：2021-10-11

    Applicant: Intel Corporation

    Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Ping Ping Ooi ,  Kooi Chi Ooi

    IPC: H01L23/66 ,  H01L21/48 ,  H01L23/498

    Abstract: An electronic circuit including a substrate having a first dielectric characteristic. The substrate can include a first side and a second side. An intermediary material can be disposed within the substrate. For instance, the intermediary material can be located between the first side and the second side. The intermediary material can include a second dielectric characteristic, where the second dielectric characteristic is different than the first dielectric characteristic. A first conductive layer can be disposed on the first side, and a second conductive layer can be disposed on the second side. A conductive path can be electrically coupled between the first conductive layer and the second conductive layer. The conductive path can be in contact with at least a portion of the intermediary material.

    Over-molded IC package with in-mold capacitor
    7.
    发明授权
    Over-molded IC package with in-mold capacitor 有权

    公开(公告)号：US10998261B2

    公开(公告)日：2021-05-04

    申请号：US15974493

    申请日：2018-05-08

    Applicant: Intel Corporation

    Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Wen Wei Lum ,  Mooi Ling Chang ,  Ping Ping Ooi

    IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56

    Abstract: Over-molded IC package assemblies including an in-mold capacitor. In some embodiments, an over-molded package assembly includes a IC chip or die coupled to one or more metal distribution layer or package substrate. A molding compound encapsulates at least the IC chip and one or more capacitors are fabricated within the molding compound. The capacitors may include two or more metal plates separated by an intervening dielectric material, all of which are embedded within a trench in the molding compound. Individual ones of the capacitor plates may physically contact a conductive land of the package redistribution layer or package substrate, for example to tie the plates to a ground plane and power plane, or two supply rails, in a decoupling capacitor application.

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