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    COUPLED INDUCTORS THROUGH SUBSTRATE-ASSEMBLY PROCESS AND/OR WAFER-LEVEL PROCESS
    114.
    发明公开
    COUPLED INDUCTORS THROUGH SUBSTRATE-ASSEMBLY PROCESS AND/OR WAFER-LEVEL PROCESS 审中-公开

    公开(公告)号：US20240304545A1

    公开(公告)日：2024-09-12

    申请号：US18182080

    申请日：2023-03-10

    Applicant: QUALCOMM Incorporated

    Inventor： Kai LIU ,  Nosun PARK ,  Jonghae KIM

    IPC: H01L23/522 ,  H01L23/538

    CPC classification number: H01L23/5227 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5386 ,  H01L28/10

    Abstract: Compact coupled inductor designs are disclosed. In an aspect, a coupled inductor comprises a pair of inductors, each inductor comprising an alternating series of metallization structures and wire bonds forming a spiral topology around a common central axis, wherein the pair of inductors are interleaved with each other along the common central axis, such that at least some of the metallization structures of one of the pair of inductors are electrically coupled with at least some of the metallization structures of the other of the pair of inductors, and at least some of the wire bonds of one of the pair of inductors are electrically coupled with at least some of the wire bonds of the other of the pair of inductors. The shapes of the wire bonds can be selected to produce a desired coupling coefficient.

    THREE-DIMENSIONAL VERTICAL CO-SPIRAL INDUCTORS
    116.
    发明公开
    THREE-DIMENSIONAL VERTICAL CO-SPIRAL INDUCTORS 审中-公开

    公开(公告)号：US20240021353A1

    公开(公告)日：2024-01-18

    申请号：US17812772

    申请日：2022-07-15

    Applicant: QUALCOMM Incorporated

    Inventor： Jonghae KIM ,  Je-Hsiung LAN ,  Kai LIU ,  Ranadeep DUTTA

    IPC: H01F17/00 ,  H01F27/28

    CPC classification number: H01F17/0013 ,  H01F27/2804 ,  H01F2027/2809

    Abstract: One or more aspects include apparatuses, systems including co-spiral inductors and methods for fabricating the same. In at least one aspect, a co-spiral inductor includes a plurality of turns, each of the plurality of turns being displaced both vertically and horizontally from a next successive turn. The plurality of turns is formed from traces on different metal layers formed on a substrate. The co-spiral inductor includes a plurality of insulators configured to electrically insulate each of the plurality of turns. The co-spiral inductor includes a plurality of interconnects configured to couple each of the plurality of turns to at least one other turn.

    CAPACITOR EMBEDDED 3D RESONATOR FOR BROADBAND FILTER
    119.
    发明公开
    CAPACITOR EMBEDDED 3D RESONATOR FOR BROADBAND FILTER 审中-公开

    公开(公告)号：US20230275004A1

    公开(公告)日：2023-08-31

    申请号：US17682868

    申请日：2022-02-28

    Applicant: QUALCOMM Incorporated

    Inventor： Jonghae KIM ,  Je-Hsiung LAN ,  Kai LIU ,  Ranadeep DUTTA

    IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H03H7/01

    CPC classification number: H01L23/481 ,  H01L23/5223 ,  H01L21/76898 ,  H03H7/0115 ,  H01L23/5227

    Abstract: An integrated circuit (IC) includes a substrate and a first through substrate via (TSV) in the substrate. The first TSV includes a first metal-insulator-metal (MIM) capacitor. The first MIM capacitor includes a first plate composed of a first metallization layer on an inner surface of the first TSV. The first MIM capacitor includes a MIM insulator layer on the first plate. The first MIM capacitor includes a second plate composed of a second metallization layer on the MIM insulator layer. The IC includes a 3D inductor. The 3D inductor includes a second TSV in the substrate. The 3D inductor includes a first trace on a first surface of the substrate, coupled to a first end of the second TSV. The 3D inductor further includes a second trace on a second surface of the substrate and coupled to a second end of the second TSV and a second end of the first TSV.

    HIGH DENSITY SILICON BASED CAPACITOR
    120.
    发明申请
    HIGH DENSITY SILICON BASED CAPACITOR 有权

    公开(公告)号：US20230092429A1

    公开(公告)日：2023-03-23

    申请号：US17483403

    申请日：2021-09-23

    Applicant: QUALCOMM Incorporated

    Inventor： Ranadeep DUTTA ,  Jonghae KIM ,  Je-Hsiung LAN

    IPC: H01L29/94 ,  H01L49/02 ,  H01L29/66 ,  H01L21/768 ,  H01L23/48

    Abstract: Disclosed are devices having a metal-insulator-metal (MIM) capacitor and methods for fabricating the devices. The MIM capacitor includes a plurality of trenches in a Silicon (Si) substrate; a porous Si surface formed in the plurality of trenches, where the porous Si surface has an irregular surface on sidewalls and bottoms of the plurality of trenches; an oxide layer conformally disposed on the porous Si surface; a first plate conformally disposed on the oxide layer; a first dielectric layer conformally disposed on the first plate; and a second plate conformally disposed on the first dielectric, where the first plate, the first dielectric layer, and the second plate, each have an irregular surface that generally conforms to the irregular surface of the porous Si surface.

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