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公开(公告)号：US11145079B2
公开(公告)日：2021-10-12
申请号：US15879281
申请日：2018-01-24
Applicant: Texas Instruments Incorporated
Inventor： Rajasekhar Reddy Allu , Niraj Nandan , Mihir Narendra Mody , Gang Hua , Brian Okchon Chae , Shashank Dabral , Hetul Sanghvi , Vikram VijayanBabu Appia , Sujith Shivalingappa
Abstract: An apparatus and method for geometrically correcting an arbitrary shaped input frame and generating an undistorted output frame. The method includes capturing arbitrary shaped input images with multiple optical devices and processing the images, identifying redundant blocks and valid blocks in each of the images, allocating an output frame with an output frame size and dividing the output frame into regions shaped as a rectangle, programming the apparatus and disabling processing for invalid blocks in each of the regions, fetching data corresponding to each of the valid blocks and storing in an internal memory, interpolating data for each of the regions with stitching and composing the valid blocks for the output frame and displaying the output frame on a display module.
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公开(公告)号：US20210209737A1
公开(公告)日：2021-07-08
申请号：US17119714
申请日：2020-12-11
Applicant: Texas Instruments Incorporated
Inventor： Gang Hua , Rajasekhar Reddy Allu , Niraj Nandan , Mihir Narendra Mody
Abstract: A method for error handling in a geometric correction engine (GCE) is provided that includes receiving configuration parameters by the GCE, generating, by the GCE in accordance with the configuration parameters, output blocks of an output frame based on corresponding blocks of an input frame, detecting, by the GCE, a run-time error during the generating, and reporting, by the GCE, an event corresponding to the run-time error.
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公开(公告)号：US20210136358A1
公开(公告)日：2021-05-06
申请号：US16669138
申请日：2019-10-30
Applicant: Texas Instruments Incorporated
Inventor： Niraj Nandan , Brian Chae , Mihir Mody , Rajasekhar Reddy Allu
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for image frame freeze detection. An example hardware accelerator includes a core logic circuit to generate second image data based on first image data associated with a first image frame, the second image data corresponding to at least one of processed image data, transformed image data, or one or more image data statistics, a load/store engine (LSE) coupled to the core logic circuit, the LSE to determine a first CRC value based on the second image data obtained from the core logic circuit, and a first interface coupled to a second interface, the second interface coupled to memory, the first interface to transmit the first CRC value obtained from the memory to a host device.
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公开(公告)号：US20210042891A1
公开(公告)日：2021-02-11
申请号：US17080884
申请日：2020-10-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rajasekhar Reddy Allu , Niraj Nandan , Mihir Narendra Mody , Gang Hua , Brian Okchon Chae , Shashank Dabral , Hetul Sanghvi , Vikram VijayanBabu Appia , Sujith Shivalingappa
Abstract: A method for geometrically correcting a distorted input frame and generating an undistorted output frame includes capturing and storing an input frame in an external memory, allocating an output frame with an output frame size and dividing the output frame into output blocks, computing a size of the input blocks in the input image corresponding to each output blocks, checking if the size of the input blocks is less than the size of the internal memory and if not dividing until the required input block size of divided sub blocks is less than the size of the internal memory, programming an apparatus with input parameters, fetching the input blocks into an internal memory, processing each of the divided sub blocks sequentially and processing the next output block in step until all the output blocks are processed; and composing the output frame for each of the blocks in the output frame.
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公开(公告)号：US10853923B2
公开(公告)日：2020-12-01
申请号：US15927820
申请日：2018-03-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rajasekhar Reddy Allu , Niraj Nandan , Mihir Narendra Mody , Gang Hua , Brian Okchon Chae , Shashank Dabral , Hetul Sanghvi , Vikram VijayanBabu Appia , Sujith Shivalingappa
Abstract: A method for geometrically correcting a distorted input frame and generating an undistorted output frame includes capturing and storing an input frame in an external memory, allocating an output frame with an output frame size and dividing the output frame into output blocks, computing a size of the input blocks in the input image corresponding to each output blocks, checking if the size of the input blocks is less than the size of the internal memory and if not dividing until the required input block size of divided sub blocks is less than the size of the internal memory, programming an apparatus with input parameters, fetching the input blocks into an internal memory, processing each of the divided sub blocks sequentially and processing the next output block in step until all the output blocks are processed; and composing the output frame for each of the blocks in the output frame.
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Patent Agency Ranking
公开(公告)号：US10652582B2
公开(公告)日：2020-05-12
申请号：US15871713
申请日：2018-01-15
Applicant: Texas Instruments Incorporated
Inventor： Niraj Nandan , Mullangi Venkata Ratna Reddy
IPC: H04N19/80 , H04N19/423 , H04N19/86
Abstract: A de-blocking filter includes a reconstructed memory that is configured to store reconstructed pixels corresponding to a current macroblock of a video image to be filtered. The current macroblock includes a set of sub-blocks, each sub-block having horizontal edges and vertical edges. An internal pixel buffer in the de-blocking filter is configured to store pixels corresponding to the set of sub-blocks from the reconstructed memory, and to store partially filtered pixels corresponding to a set of partially filtered macroblocks. An edge order controller in the de-blocking filter is configured to load the pixels corresponding to the set of sub-blocks into a filter engine from the internal pixel buffer, to filter the set of sub-blocks, such that, at least one horizontal edge is filtered before filtering all vertical edges of the set of sub-blocks.
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公开(公告)号：US10455238B2
公开(公告)日：2019-10-22
申请号：US15853474
申请日：2017-12-22
Applicant: Texas Instruments Incorporated
Inventor： Mihir Narendra Mody , Niraj Nandan , Hideo Tamama
IPC: H04N19/176 , H04N19/117 , H04N19/14 , H04N19/82 , H04N19/86 , H04N19/186
Abstract: A method of de-blocking filtering a processed video is provided. The processed video includes a plurality of blocks and each block includes a plurality of sub-blocks. A current block of the plurality of blocks includes vertical edges and horizontal edges. The processed video further includes a set of control parameters and reconstructed pixels corresponding to the current block. A boundary strength index is estimated at the vertical edges and at the horizontal edges of the current block. The set of control parameters, the reconstructed pixels corresponding to the current block and partially filtered pixels corresponding to a set of adjacent sub-blocks are loaded. The vertical edges and the horizontal edges of the current block are filtered based on the boundary strength index and the set of control parameters such that a vertical edge of the current block is filtered before filtering at least one horizontal edge of the current block.
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公开(公告)号：US20190235927A1
公开(公告)日：2019-08-01
申请号：US16377966
申请日：2019-04-08
Applicant: Texas Instruments Incorporated
Inventor： Niraj Nandan , Hetul Sanghvi , Mihir Narendra Mody
CPC classification number: G06F9/5044 , G06F5/12 , G06F9/4881 , G06F9/4887 , G06F9/52 , G06F9/522 , G06F9/544 , G06F11/0757 , G06T1/20
Abstract: A hardware thread scheduler (HTS) is provided for a multiprocessor system. The HTS is configured to schedule processing of multiple threads of execution by resolving data dependencies between producer modules and consumer modules for each thread. Pattern adaptors may be provided in the scheduler that allows mixing of multiple data patterns across blocks of data. Transaction aggregators may be provided that allow re-using the same image data by multiple threads of execution while the image date remains in a given data buffer. Bandwidth control may be provided using programmable delays on initiation of thread execution. Failure and hang detection may be provided using multiple watchdog timers.
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公开(公告)号：US20190096041A1
公开(公告)日：2019-03-28
申请号：US15714862
申请日：2017-09-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rajasekhar Reddy Allu , Niraj Nandan , Mihir Narendra Mody , Gang Hua , Brian Okchon Chae , Shashank Dabral , Hetul Sanghvi , Vikram VijayanBabu Appia , Sujith Shivalingappa
Abstract: An apparatus and method for geometrically correcting a distorted input frame and generating an undistorted output frame. The apparatus includes an external memory block that stores the input frame, a counter block to compute output coordinates of the output frame for a region based on a block size of the region, a back mapping block to generate input coordinates corresponding to each of the output coordinates, a bounding module to compute input blocks corresponding to each of the input coordinates, a buffer module to fetch data corresponding to each of the input blocks, an interpolation module to interpolate data from the buffer module and a display module that receives the interpolated data for each of the regions and stitch an output image. The method includes determining the size of the output block based on a magnification data.
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公开(公告)号：US20180184125A1
公开(公告)日：2018-06-28
申请号：US15871713
申请日：2018-01-15
Applicant: Texas Instruments Incorporated
Inventor： Niraj Nandan , Mullangi Venkata Ratna Reddy
IPC: H04N19/80 , H04N19/423 , H04N19/86
CPC classification number: H04N19/80 , H04N19/423 , H04N19/86
Abstract: A de-blocking filter includes a reconstructed memory that is configured to store reconstructed pixels corresponding to a current macroblock of a video image to be filtered. The current macroblock includes a set of sub-blocks, each sub-block having horizontal edges and vertical edges. An internal pixel buffer in the de-blocking filter is configured to store pixels corresponding to the set of sub-blocks from the reconstructed memory, and to store partially filtered pixels corresponding to a set of partially filtered macroblocks. An edge order controller in the de-blocking filter is configured to load the pixels corresponding to the set of sub-blocks into a filter engine from the internal pixel buffer, to filter the set of sub-blocks, such that, at least one horizontal edge is filtered before filtering all vertical edges of the set of sub-blocks.
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