公开(公告)号：US07701040B2

公开(公告)日：2010-04-20

申请号：US11860377

申请日：2007-09-24

Applicant: Rui Huang ,  Yaojian Lin ,  Seng Guan Chow

Inventor： Rui Huang ,  Yaojian Lin ,  Seng Guan Chow

IPC: H01L23/552

CPC classification number: H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/552 ,  H01L24/05 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/48 ,  H01L24/81 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05556 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/0665 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A wafer level semiconductor package has a substrate and an RF module and baseband module coupled to the substrate with solder bumps. An underfill material is disposed under the RF module and baseband module. A first shielding layer is applied to a first surface of the substrate. A seed layer is deposited on the substrate and RF module and baseband module. A second shielding layer is plated over the seed layer, except over the contact pads on the substrate. The second shielding layer can be made from copper, gold, nickel, or aluminum. The first and second shielding layers substantially cover the wafer level semiconductor package to isolate the baseband module from electromagnetic interference generated by the RF module. The first and second shielding layers are grounded through the substrate.

Abstract translation: 晶片级半导体封装具有衬底和RF模块以及基板模块，该模块和基板模块通过焊料凸块耦合到衬底。 在RF模块和基带模块之下设置底部填充材料。 第一屏蔽层被施加到基板的第一表面。 种子层沉积在基板和RF模块和基带模块上。 除了衬底上的接触焊盘之外，在种子层上电镀第二屏蔽层。 第二屏蔽层可以由铜，金，镍或铝制成。 第一和第二屏蔽层基本上覆盖晶片级半导体封装以将基带模块与由RF模块产生的电磁干扰隔离。 第一和第二屏蔽层通过衬底接地。

公开(公告)号：US07691747B2

公开(公告)日：2010-04-06

申请号：US11947617

申请日：2007-11-29

Applicant: Yaojian Lin ,  Haijing Cao ,  Qing Zhang Zhang ,  Kang Chen ,  Jianmin Fang

Inventor： Yaojian Lin ,  Haijing Cao ,  Qing Zhang Zhang ,  Kang Chen ,  Jianmin Fang

IPC: H01L21/44

CPC classification number: H01L25/16 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L25/0652 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/2518 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2224/05599

Abstract: A semiconductor wafer contains a substrate having a plurality of active devices formed thereon. An analog circuit is formed on the substrate. The analog circuit can be an inductor, metal-insulator-metal capacitor, or resistor. The inductor is made with copper. A through substrate via (TSV) is formed in the substrate. A conductive material is deposited in the TSV in electrical contact with the analog circuit. An under bump metallization layer is formed on a backside of the substrate in electrical contact with the TSV. A solder material is deposited on the UBM layer. The solder material is reflowed to form a solder bump. A wire bond is formed on a top surface of the substrate. A redistribution layer is formed between the TSV and UBM. The analog circuit electrically connects through the TSV to the solder bump on the back side of the substrate.

Abstract translation: 半导体晶片包含其上形成有多个有源器件的衬底。 在基板上形成模拟电路。 模拟电路可以是电感，金属 - 绝缘体 - 金属电容或电阻。 电感由铜制成。 在衬底中形成贯穿衬底通孔（TSV）。 导电材料沉积在与模拟电路电接触的TSV中。 在与TSV电接触的衬底的背面上形成凸起下金属化层。 焊料材料沉积在UBM层上。 焊料材料被回流以形成焊料凸块。 在基板的顶表面上形成引线接合。 在TSV和UBM之间形成再分配层。 模拟电路通过TSV电连接到衬底背面的焊料凸块。

公开(公告)号：US20090309212A1

公开(公告)日：2009-12-17

申请号：US12481404

申请日：2009-06-09

Applicant: Il Kwon Shim ,  Seng Guan Chow ,  Yaojian Lin

Inventor： Il Kwon Shim ,  Seng Guan Chow ,  Yaojian Lin

IPC: H01L23/482 ,  H01L21/50

CPC classification number: H01L23/562 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/19 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/48091 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/81805 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by forming a first conductive layer over a sacrificial carrier. A conductive pillar is formed over the first conductive layer. An active surface of a semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the conductive pillar. The carrier and adhesive layer are removed. A stress relief insulating layer is formed over the active surface of the semiconductor die and a first surface of the encapsulant. The stress relief insulating layer has a first thickness over the semiconductor die and a second thickness less than the first thickness over the encapsulant. A first interconnect structure is formed over the stress relief insulating layer. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillar.

Abstract translation: 通过在牺牲载体上形成第一导电层制成半导体器件。 在第一导电层上形成导电柱。 半导体管芯的有源表面安装在载体上。 密封剂沉积在半导体管芯上方并围绕导电柱。 去除载体和粘合剂层。 在半导体管芯的有源表面和密封剂的第一表面上形成应力消除绝缘层。 应力消除绝缘层在半导体管芯上方具有第一厚度，并且第二厚度小于密封剂上的第一厚度。 在应力消除绝缘层上形成第一互连结构。 在与第一互连结构相对的密封剂的第二表面上形成第二互连结构。 第一和第二互连结构通过导电柱电连接。

公开(公告)号：US20090032975A1

公开(公告)日：2009-02-05

申请号：US12182283

申请日：2008-07-30

Applicant: Byung Tai Do ,  Stephen A. Murphy ,  Yaojian Lin ,  Heap Hoe Kuan ,  Pandi Chelvam Marimuthu ,  Hin Hwa Goh

Inventor： Byung Tai Do ,  Stephen A. Murphy ,  Yaojian Lin ,  Heap Hoe Kuan ,  Pandi Chelvam Marimuthu ,  Hin Hwa Goh

IPC: H01L23/49 ,  H01L21/44

CPC classification number: H01L24/16 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/1411 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48711 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2224/85 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2224/48811 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012

Abstract: A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer.

Abstract translation: 半导体晶片包含多个半导体管芯。 晶片具有在其表面上形成的接触垫。 在晶片上形成钝化层。 在钝化层上形成应力缓冲层。 将应力缓冲层图案化以暴露接触焊盘。 金属层沉积在应力缓冲层上。 金属层是用于与接触焊盘电接触的半导体器件的公共电压总线。 在与接触垫电接触的晶片之上形成粘合层，阻挡层和种子层。 金属层安装到种子层。 焊料凸块或其它互连结构形成在金属层上。 在金属层上形成第二钝化层。 在替代实施例中，可以将金属层沉积在金属层上，并且连接到金属层的引线键。

公开(公告)号：US20090001509A1

公开(公告)日：2009-01-01

申请号：US11770690

申请日：2007-06-28

Applicant: Yaojian Lin

Inventor： Yaojian Lin

IPC: H01L27/01 ,  H01L21/77

CPC classification number: H01L27/016 ,  H01L21/77 ,  H05K1/162 ,  H05K1/167 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/09845

Abstract: A circuit system includes: forming a first electrode over a substrate; applying a dielectric layer over the first electrode and the substrate; forming a second electrode over the dielectric layer; and forming a dielectric structure from the dielectric layer with the dielectric structure within a first horizontal boundary of the first electrode.

Abstract translation: 电路系统包括：在衬底上形成第一电极; 在第一电极和衬底上施加电介质层; 在所述电介质层上形成第二电极; 以及在所述第一电极的第一水平边界内从具有所述电介质结构的介电层形成电介质结构。

公开(公告)号：US07381634B2

公开(公告)日：2008-06-03

申请号：US10907732

申请日：2005-04-13

Applicant: Yaojian Lin ,  Byung Tai Do ,  Wan Lay Looi ,  Haijing Cao

Inventor： Yaojian Lin ,  Byung Tai Do ,  Wan Lay Looi ,  Haijing Cao

IPC: H01L21/44

CPC classification number: H01L24/02 ,  C23F1/26 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01072 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/48

Abstract: An integrated circuit system provides a precursor for an integrated wire bond and flip chip structure. The precursor has a plurality of contact pads thereon. A layer of titanium is deposited on the precursor. A layer of nickel-vanadium is deposited on the layer of titanium. A layer of copper is deposited on the layer of nickel-vanadium. A mask is formed on at least a portion of the layer of copper. Portions of the layers of copper and nickel-vanadium not protected by the mask are removed to expose portions of the layer of titanium. The exposed portions of the layer of titanium are etched with an etching solution consisting of an etchant, a viscosity modifier, and an oxidizer.

Abstract translation: 集成电路系统为集成引线键合和倒装芯片结构提供了前体。 前体在其上具有多个接触焊盘。 一层钛沉积在前体上。 一层镍钒沉积在钛层上。 一层铜沉积在镍 - 钒层上。 在铜层的至少一部分上形成掩模。 去除未被掩模保护的部分铜和镍钒层以露出钛层的部分。 用蚀刻剂，粘度调节剂和氧化剂组成的蚀刻溶液蚀刻钛层的暴露部分。

公开(公告)号：US20070114639A1

公开(公告)日：2007-05-24

申请号：US11556035

申请日：2006-11-02

Applicant: Yaojian Lin ,  Romeo Alvarez ,  Haijing Cao ,  Wan Lay Looi

Inventor： Yaojian Lin ,  Romeo Alvarez ,  Haijing Cao ,  Wan Lay Looi

IPC: H01L23/495

CPC classification number: H01L24/10 ,  H01L23/3114 ,  H01L24/13 ,  H01L2224/05008 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: An integrated circuit package system includes an integrated circuit, and forming a patterned redistribution pad over the integrated circuit.

Abstract translation: 集成电路封装系统包括集成电路，并在该集成电路上形成图案化再分配焊盘。

公开(公告)号：US09620455B2

公开(公告)日：2017-04-11

申请号：US12822458

申请日：2010-06-24

Applicant: Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo

Inventor： Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo

IPC: H01L21/00 ,  H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/13 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/21 ,  H01L2224/2105 ,  H01L2224/215 ,  H01L2224/22 ,  H01L2224/221 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/09701 ,  H01L2924/1203 ,  H01L2924/12041 ,  H01L2924/1304 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15172 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/01014 ,  H01L2924/0665 ,  H01L2924/0105 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor wafer contains a plurality of semiconductor die with bumps formed over contact pads on an active surface of the semiconductor die. An ACF is deposited over the bumps and active surface of the wafer. An insulating layer can be formed between the ACF and semiconductor die. The semiconductor wafer is singulated to separate the die. The semiconductor die is mounted to a temporary carrier with the ACF oriented to the carrier. The semiconductor die is forced against the carrier to compress the ACF under the bumps and form a low resistance electrical interconnect to the bumps. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected through the compressed ACF to the bumps. The ACF reduces shifting of the semiconductor die during encapsulation.

公开(公告)号：US09484259B2

公开(公告)日：2016-11-01

申请号：US13239080

申请日：2011-09-21

Applicant: Yaojian Lin ,  Kang Chen ,  Jianmin Fang

Inventor： Yaojian Lin ,  Kang Chen ,  Jianmin Fang

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L21/76898 ,  H01L21/481 ,  H01L21/486 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0347 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/0554 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/48091 ,  H01L2224/73104 ,  H01L2224/73265 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01007 ,  H01L2924/01023 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.

公开(公告)号：US09385009B2

公开(公告)日：2016-07-05

申请号：US13243558

申请日：2011-09-23

Applicant: Yaojian Lin ,  Rui Huang ,  Kang Cheng ,  Gu Yu

Inventor： Yaojian Lin ,  Rui Huang ,  Kang Cheng ,  Gu Yu

IPC: H01L29/41 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L23/3128 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/568 ,  H01L23/293 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/92144 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2224/19 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over the encapsulant and semiconductor die. First vias are formed through the first insulating layer to expose contact pads of the semiconductor die. A first conductive layer is formed over the first insulating layer and into the first vias to electrically connect to the contact pads of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. Second vias are formed through the second insulating layer by laser direct ablation and aligned or offset with the first vias to expose the first conductive layer. A second conductive layer is formed over the second insulating layer and into the second vias. Conductive vias can be formed through the encapsulant.

Abstract translation: 半导体器件具有安装到载体上的半导体管芯。 密封剂沉积在半导体管芯和载体上。 载体被移除。 在密封剂和半导体管芯上形成第一绝缘层。 通过第一绝缘层形成第一通孔以暴露半导体管芯的接触焊盘。 第一导电层形成在第一绝缘层上并且形成在第一通孔中，以电连接到半导体管芯的接触焊盘。 在第一绝缘层和第一导电层上形成第二绝缘层。 通过激光直接消融通过第二绝缘层形成第二通孔，并与第一通孔对准或偏移以暴露第一导电层。 第二导电层形成在第二绝缘层上并进入第二通孔中。 可以通过密封剂形成导电孔。