公开(公告)号：US11786930B2

公开(公告)日：2023-10-17

申请号：US16466743

申请日：2017-12-12

Applicant: HZO, Inc.

Inventor： Shailendra Vikram Singh ,  Gianfranco Aresta ,  Andrew Simon Hall Brooks ,  Siobhan Marie Woollard ,  Gareth Hennighan

IPC: B05D1/00 ,  B05D7/00 ,  C09D127/20 ,  C09D183/04 ,  H05K3/28 ,  B05D3/04

CPC classification number: B05D1/62 ,  B05D7/50 ,  C09D127/20 ,  C09D183/04 ,  H05K3/285 ,  B05D3/0486 ,  B05D2252/04 ,  B05D2451/00 ,  B05D2518/10 ,  H05K2201/0179 ,  H05K2201/09872 ,  H05K2203/095 ,  H05K2203/1322 ,  H05K2203/1338

Abstract: A method for depositing a protective coating onto a substrate, wherein the protective coating comprises (i) a moisture-barrier layer which is in contact with the substrate and which comprises a first sub-layer, optionally one or more intermediate sub-layers, and a final sub-layer, (ii) a mechanical-protective layer which is inorganic, and (iii) a gradient layer interposing the moisture-barrier layer and the mechanical-protective layer.

公开(公告)号：US20180240599A1

公开(公告)日：2018-08-23

申请号：US15899403

申请日：2018-02-20

Applicant: TDK CORPORATION

Inventor： Koichi TSUNODA ,  Mitsuhiro TOMIKAWA ,  Kazuhiro YOSHIKAWA ,  Kenichi YOSHIDA

IPC: H01G4/33 ,  H01G9/04 ,  H01G9/012 ,  H01G9/07

CPC classification number: H01G4/33 ,  H01G2/02 ,  H01G4/224 ,  H01G4/228 ,  H01G9/012 ,  H01G9/04 ,  H01G9/07 ,  H05K2201/0179 ,  H05K2201/0195

Abstract: In a thin-film capacitor, an electrode terminal layer is divided into a plurality of parts by a penetration portion, and includes a frame portion as one divided part. The frame portion is disposed along an outer edge of the electrode terminal layer when viewed from the bottom surface side of the electrode terminal layer, and the frame portion can hinder deformation of the electrode terminal layer stretching or warping in a thickness direction or an in-plane direction, whereby such deformation can be prevented. Accordingly, in the thin-film capacitor, the electrode terminal layer is not likely to be deformed and an improvement in strength thereof is achieved.

公开(公告)号：US09947850B2

公开(公告)日：2018-04-17

申请号：US15124724

申请日：2015-02-27

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiro Konishi ,  Shin Itoh ,  Hiroyuki Nokubo ,  Yoshiaki Itakura

IPC: H01L29/49 ,  H01L33/64 ,  H05K1/05 ,  H01L25/075 ,  H01L33/56 ,  H01L33/60 ,  H01L33/62 ,  F21K9/00 ,  F21V29/77 ,  H05K3/44 ,  F21Y105/10 ,  F21Y115/10

CPC classification number: H01L33/642 ,  F21K9/00 ,  F21V29/773 ,  F21Y2105/10 ,  F21Y2115/10 ,  H01L25/0753 ,  H01L33/56 ,  H01L33/60 ,  H01L33/62 ,  H01L33/641 ,  H01L2224/16225 ,  H01L2933/005 ,  H01L2933/0058 ,  H01L2933/0066 ,  H01L2933/0075 ,  H05K1/053 ,  H05K3/44 ,  H05K2201/0179 ,  H05K2201/10106

Abstract: In order to provide a substrate for light emitting devices having high heat radiating properties, dielectric strength voltage properties, light reflectivity, and excellent mass productivity, a substrate (5) includes an intermediate layer (11) containing ceramic which is formed on the surface of the aluminum base (10) by using an aerosol deposition method.

公开(公告)号：US20170245358A1

公开(公告)日：2017-08-24

申请号：US15501839

申请日：2015-08-04

Applicant: AT & S Austria Technologie & Systemtechnik Aktiengesellschaft

Inventor： Elisabeth Kreutzwiesner ,  Gernot Schulz

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/22 ,  C23C16/27 ,  H01L23/373 ,  H01L21/48 ,  C23C14/06 ,  C23C14/34 ,  H05K1/09 ,  H01L23/498

CPC classification number: H05K1/0204 ,  B32B5/00 ,  B32B5/02 ,  B32B5/28 ,  B32B7/00 ,  B32B7/02 ,  B32B7/12 ,  B32B9/00 ,  B32B15/00 ,  B32B15/04 ,  B32B15/20 ,  B32B27/06 ,  B32B27/18 ,  B32B2264/00 ,  B32B2264/10 ,  B32B2264/102 ,  B32B2307/20 ,  B32B2307/202 ,  B32B2307/206 ,  B32B2307/30 ,  B32B2307/302 ,  B32B2457/00 ,  B32B2457/08 ,  C23C14/0611 ,  C23C14/34 ,  C23C16/276 ,  H01L21/4846 ,  H01L23/373 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H05K1/0203 ,  H05K1/0206 ,  H05K1/0313 ,  H05K1/09 ,  H05K1/115 ,  H05K3/022 ,  H05K3/22 ,  H05K3/4655 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/0323 ,  H05K2201/0358

Abstract: A composite structure for use as a constituent of a mounting device, wherein the composite structure comprises an electrically conductive carrier, an intermediate layer comprising adhesion promoting material and being arranged on the electrically conductive carrier, and a thermally conductive and electrically insulating layer on the intermediate layer.

公开(公告)号：US20170174915A1

公开(公告)日：2017-06-22

申请号：US14971595

申请日：2015-12-16

Applicant: US of America as Represented by the Administrator of the National Aeronautics and Space Administrati

Inventor： Terry D. Rolin ,  Curtis W. Hill

IPC: C09D11/033 ,  H01G13/04 ,  C09D11/14

CPC classification number: C09D11/033 ,  C08K3/22 ,  C08K3/24 ,  C08K3/40 ,  C08K9/02 ,  C08K2003/2206 ,  C08K2003/2237 ,  C08K2201/003 ,  C08K2201/011 ,  C09D11/037 ,  C09D11/14 ,  C09D11/322 ,  C09D11/36 ,  H01G4/12 ,  H01G4/129 ,  H01G4/30 ,  H01G4/33 ,  H01G13/04 ,  H05K1/162 ,  H05K2201/0179 ,  H05K2201/0209 ,  H05K2203/0776

Abstract: The present invention is a dielectric ink and means for printing using said ink. Approximately 10-20% of the ink is a custom organic vehicle made of a polar solvent and a binder. Approximately 30-70% of the ink is a dielectric powder having an average particle diameter of approximately 10-750 nm. Approximately 5-15% of the ink is a dielectric constant glass. Approximately 10-35% of the ink is an additional amount of solvent. The ink is deposited on a printing substrate to form at least one printed product, which is then dried and cured to remove the solvent and binder, respectively. The printed product then undergoes sintering in an inert gas atmosphere.

公开(公告)号：US09572258B2

公开(公告)日：2017-02-14

申请号：US11027386

申请日：2004-12-30

Applicant: Sriram Srinivasan ,  John S. Guzek ,  Cengiz A. Palanduz ,  Victor Prokofiev ,  Joel A. Auernheimer

Inventor： Sriram Srinivasan ,  John S. Guzek ,  Cengiz A. Palanduz ,  Victor Prokofiev ,  Joel A. Auernheimer

IPC: H05K3/36 ,  H05K1/16 ,  H01G4/10 ,  H01G4/12 ,  H01G4/33 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K1/162 ,  H01G4/10 ,  H01G4/1209 ,  H01G4/33 ,  H05K3/429 ,  H05K3/4611 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09309 ,  Y10T29/43 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a substrate core by attaching a first dielectric layer to a second conductive layer of a thin film capacitor, and attaching a second dielectric layer to a first conductive layer of the thin film capacitor.

Abstract translation: 描述形成微电子结构的方法。 这些方法的实施例包括通过将第一电介质层附着到薄膜电容器的第二导电层并且将第二电介质层附接到薄膜电容器的第一导电层来形成衬底芯。

公开(公告)号：US20150291830A1

公开(公告)日：2015-10-15

申请号：US14442944

申请日：2013-11-14

Applicant: LIQUIPEL IP LLC

Inventor： Herbert Vincent Galbreath ,  Alexander Hill ,  Daniel Storey

IPC: C09D133/16 ,  C23C16/505 ,  H05K3/28 ,  H01L21/02 ,  H01L21/56 ,  C23C16/50 ,  D06M15/256

CPC classification number: C09D133/16 ,  B05D1/12 ,  B05D1/62 ,  C08F2/52 ,  C23C16/50 ,  C23C16/505 ,  D06M10/10 ,  D06M15/277 ,  D06M23/08 ,  D06M2200/12 ,  H01L21/02118 ,  H01L21/02274 ,  H01L21/56 ,  H05K3/28 ,  H05K3/285 ,  H05K2201/0108 ,  H05K2201/0179 ,  H05K2203/095 ,  Y10T428/24975 ,  Y10T428/254 ,  Y10T442/2123

Abstract: Apparatuses and methods are described that involve the deposition of polymer coatings on substrates. The polymer coatings generally comprise an electrically insulating layer and/or a hydrophobic layer. The hydrophobic layer can comprise fused polymer particles have an average primary particle diameter on the nanometer to micrometer scale. The polymer coatings are deposited on substrates using specifically adapted plasma enhanced chemical vapor deposition approaches. The substrates can include computing devices and fabrics.

Abstract translation: 描述了涉及在基底上沉积聚合物涂层的装置和方法。 聚合物涂层通常包括电绝缘层和/或疏水层。 疏水层可包含熔融聚合物颗粒，其平均初级粒径为纳米至微米级。 使用特别适合的等离子体增强化学气相沉积方法将聚合物涂层沉积在基板上。 基板可以包括计算设备和织物。

公开(公告)号：US20150264813A1

公开(公告)日：2015-09-17

申请号：US14204898

申请日：2014-03-11

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H05K1/18 ,  H05K3/46 ,  H05K1/02 ,  H05K1/16 ,  H05K1/11

CPC classification number: H05K1/162 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/5223 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/165 ,  H05K1/167 ,  H05K3/4673 ,  H05K2201/0179 ,  H05K2201/09254 ,  H05K2201/09263 ,  H05K2201/09672 ,  H05K2201/09763 ,  H05K2201/10378

Abstract: A chip-stack interposer structure including a passive device is described, including an interposing layer, a capacitor, a first contact and a second contact. The capacitor is embedded in or disposed on the interposing layer, including a first electrode, a second electrode and a dielectric layer between the first and the second electrodes. The first contact is connected with the first electrode. The second contact is connected with the second electrode. The first electrode and the second electrode are disposed at the same side of the interposing layer or at different sides of the interposing layer.

Abstract translation: 描述包括无源器件的芯片堆叠插入器结构，包括中介层，电容器，第一接触和第二接触。 电容器嵌入或设置在插入层上，包括在第一和第二电极之间的第一电极，第二电极和介电层。 第一触点与第一电极连接。 第二触点与第二电极连接。 第一电极和第二电极设置在插入层的相同侧或者插入层的不同侧。

公开(公告)号：US08857050B2

公开(公告)日：2014-10-14

申请号：US12533503

申请日：2009-07-31

Applicant: John M. Bedinger ,  Michael A. Moore

Inventor： John M. Bedinger ,  Michael A. Moore

IPC: H05K3/30 ,  H05K3/28 ,  H01L23/482 ,  H01L23/31 ,  H01L23/00

CPC classification number: H05K3/284 ,  H01L23/3192 ,  H01L23/4821 ,  H01L24/83 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/8592 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/0781 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19041 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2203/1322 ,  Y10T29/49124 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49982 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/29075 ,  H01L2924/00014

Abstract: A method includes providing a circuit board having an outer surface, the outer surface configured with a plurality of discrete electrical components that are each manufactured independently of one another, and coating the outer surface and the plurality of discrete electrical components with a first protective dielectric layer. The method further includes coating the first protective dielectric layer with a second dielectric layer. The second dielectric layer includes a dielectric material having a modulus of elasticity less than 3.5 Giga-Pascal (GPa), a dielectric constant less than 2.7, a dielectric loss less than 0.002, a breakdown voltage strength in excess of 2 million volts/centimeter (MV/cm), a temperature stability to 3000 Celsius, a defect densities less than 0.5/centimeter, a pinhole free in films greater than 50 Angstroms, and is capable of being deposited conformally over and under 3D structures with thickness uniformity less than or equal to 10%.

Abstract translation: 一种方法包括提供具有外表面的电路板，所述外表面配置有彼此独立制造的多个分立电气部件，并且用第一保护介电层涂覆所述外表面和所述多个离散电部件 。 该方法还包括用第二介电层涂覆第一保护介电层。 第二电介质层包括弹性模量小于3.5千兆帕（GPa），介电常数小于2.7的介电材料，介电损耗小于0.002，击穿电压强度超过2百万伏/厘米（ MV / cm），温度稳定度为3000摄氏度，缺陷密度小于0.5 /厘米，薄膜中大小不超过50埃的针孔，并且能够在厚度均匀度小于或等于3维的3D结构下保形地沉积 至10％。

公开(公告)号：US20140293564A1

公开(公告)日：2014-10-02

申请号：US14202140

申请日：2014-03-10

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kei MURAYAMA ,  Mitsuhiro AIZAWA ,  Koji HARA

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/0271 ,  H01L21/563 ,  H01L23/00 ,  H01L23/13 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/0306 ,  H05K3/4061 ,  H05K3/467 ,  H05K3/4688 ,  H05K2201/0179 ,  H05K2201/068 ,  H05K2201/10378 ,  H01L2924/00

Abstract: An interposer includes a wiring member including a first inorganic substrate, a reinforcement member including a second inorganic substrate, and an adhesive part interposed between the wiring member and the reinforcement member. Each of the first and second inorganic substrates includes first and second surfaces. Multiple inorganic insulating layers formed on the first surface of each of the first and second inorganic substrates have the same layer configuration and are arranged symmetrically in a vertical direction with the adhesive part centered therebetween. An inorganic insulating layer and an organic insulating layer formed on the second surface of each of the first and second inorganic substrates have the same layer configuration and are arranged symmetrically in the vertical direction with the adhesive part. An organic insulating layer formed on the second surface of each of the first and second inorganic substrates is an outermost insulating layer.

Abstract translation: 插入件包括布线构件，该布线构件包括第一无机基板，包括第二无机基板的加强构件和插入在布线构件和加强构件之间的粘合部。 第一和第二无机基材中的每一个包括第一和第二表面。 形成在第一和第二无机基板的每一个的第一表面上的多个无机绝缘层具有相同的层构造，并且在粘合剂部分居中的同时在垂直方向上对称地布置。 形成在第一和第二无机基板的第二表面上的无机绝缘层和有机绝缘层具有相同的层构造，并且在垂直方向上与粘合部对称地配置。 形成在第一和第二无机基板的第二表面上的有机绝缘层是最外层的绝缘层。