公开(公告)号：US20200027826A1

公开(公告)日：2020-01-23

申请号：US16587270

申请日：2019-09-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： CHIEN-HSIN LEE ,  HAOJUN ZHANG ,  MAHADEVA IYER NATARAJAN

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/60

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to transistor structures and methods of manufacture. The structure includes active metal lines separated by electrically floating metal layers which have a width less than a width of the active metal lines.

公开(公告)号：US20200026000A1

公开(公告)日：2020-01-23

申请号：US16040896

申请日：2018-07-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/132 ,  G02B6/136

Abstract: Structures including a waveguide arrangement and methods of fabricating a structure that includes a waveguide arrangement. A second waveguide spaced in a lateral direction from a first waveguide, a third waveguide spaced in a vertical direction from the first waveguide, and a fourth waveguide spaced in the vertical direction from the second waveguide. The third waveguide is arranged in the lateral direction to provide a first overlapping relationship with the first waveguide. The fourth waveguide is arranged in the lateral direction to provide a second overlapping relationship with the second waveguide.

公开(公告)号：US20200020388A1

公开(公告)日：2020-01-16

申请号：US16031439

申请日：2018-07-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Igor Arsovski ,  Akhilesh Patil ,  Eric D. Hunt-Schroeder

IPC: G11C11/419 ,  G11C7/12 ,  G11C11/4076 ,  G11C11/4074

Abstract: The present disclosure relates to a structure including a sequential mode read controller which is configured to receive a sequential read enable burst signal and a starting word line address, identify consecutive read operations from an array of storage cells accessed via a plurality of word lines, precharge a plurality of bit lines of the storage cells no more than once during the consecutive read operations, and hold a word line of the word lines active throughout the consecutive read operations. The sequential read enable burst signal and a starting word line address are decoded to select a row address and activate the corresponding word line from a plurality of word lines in the array.

公开(公告)号：US10535771B1

公开(公告)日：2020-01-14

申请号：US16016828

申请日：2018-06-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Laertis Economikos ,  Shesh Mani Pandey ,  Hui Zang ,  Haiting Wang ,  Jinping Liu

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L29/423 ,  H01L21/02

Abstract: A method of forming transistor devices with an air gap in the replacement gate structure is disclosed including forming a placeholder gate structure above a semiconductor material region, forming a sidewall spacer adjacent the placeholder gate structure, removing the placeholder gate structure to define a gate cavity bounded by the sidewall spacer, forming a gate insulation layer in the gate cavity, the gate insulation layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, forming a gate electrode in the gate cavity above the gate insulation layer, removing at least a portion of the second portion of the gate insulation layer to define an air gap cavity adjacent the gate electrode, and forming a first gate cap layer above the gate electrode, wherein the first gate cap layer seals an upper end of the air gap cavity.

公开(公告)号：US10535674B2

公开(公告)日：2020-01-14

申请号：US15653661

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juergen Faul ,  Frank Jakubowski

IPC: H01L27/11568 ,  H01L21/762 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/265 ,  H01L27/11521 ,  H01L27/12 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11582 ,  H01L49/02

Abstract: A semiconductor device structure includes a hybrid substrate having a semiconductor-on-insulator (SOI) region that includes an active semiconductor layer, a substrate material and a buried insulating material interposed between the active semiconductor layer and the substrate material, and a bulk semiconductor region that includes the substrate material. An insulating structure is positioned in the hybrid substrate, wherein the insulating structure separates the bulk region from the SOI region, and a gate electrode is positioned above the substrate material in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.

公开(公告)号：US10535379B2

公开(公告)日：2020-01-14

申请号：US15695457

申请日：2017-09-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Darren L. Anand ,  John A. Fifield ,  Eric D. Hunt-Schroeder ,  Mark D. Jacunski

IPC: G11C7/06 ,  G11C17/18

Abstract: A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.

公开(公告)号：US20200013684A1

公开(公告)日：2020-01-09

申请号：US16538041

申请日：2019-08-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Soss ,  Steven Bentley

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/768 ,  H01L29/08

Abstract: The present disclosure is directed to various embodiments of a product that includes first and second vertical semiconductor structures for first and second, respectively, vertical transistor devices, and first and second gate structures positioned adjacent the first and second, respectively, vertical semiconductor structures. The product also includes a shared conductive gate plug positioned laterally between the first gate structure and the second gate structure, wherein the shared conductive gate plug is conductively coupled to both the first gate structure and the second gate structure.

公开(公告)号：US20200013678A1

公开(公告)日：2020-01-09

申请号：US16026130

申请日：2018-07-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sipeng Gu ,  Akshey Sehgal ,  Xinyuan Dou ,  Sunil K. Singh ,  Ravi P. Srivastava ,  Haiting Wang ,  Scott H. Beasor

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L23/48 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/49 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/66

Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap.

公开(公告)号：US20200013551A1

公开(公告)日：2020-01-09

申请号：US16550431

申请日：2019-08-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sunil K. Singh ,  Jagar Singh

IPC: H01F41/063 ,  H01F41/12 ,  H01F5/00 ,  H01F5/06 ,  H01F41/34 ,  H01F17/00 ,  H01F41/04 ,  H01L49/02 ,  H01L21/00

Abstract: A first layer on a substrate includes an insulator material portion adjacent an energy-reactive material portion. The energy-reactive material portion evaporates upon application of energy during manufacturing. Processing patterns the first layer to include recesses extending to the substrate in at least the energy-reactive material portion. The recesses are filled with a conductor material, and a porous material layer is formed on the first layer and on the conductor material. Energy is applied to the porous material layer to: cause the energy to pass through the porous material layer and reach the energy-reactive material portion; cause the energy-reactive material portion to evaporate; and fully remove the energy-reactive material portion from an area between the substrate and the porous material layer, and this leaves a void between the substrate and the porous material layer and adjacent to the conductor material.

公开(公告)号：US20200012252A1

公开(公告)日：2020-01-09

申请号：US16029759

申请日：2018-07-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Richard P. Good ,  Eyup Cinar

IPC: G05B19/401

Abstract: A method for initializing individual exposure field parameters of an overlay controller is disclosed including initializing a first control thread having a first context associated with a first product type, wherein a first layout of first exposure fields is defined for the first product type for processing in a stepper. The method further includes remapping a set of previous control state data for a set of control threads associated with other product types different than the first product type into the first layout. The other product types have layouts of second exposure fields different than the first layout. An initial set of control state data for the first control thread associated with the first product type is generated using the remapped previous control state data. The stepper is configured for processing a first substrate of the first product type using the initial set of control state data.