公开(公告)号：US20160344644A1

公开(公告)日：2016-11-24

申请号：US15226045

申请日：2016-08-02

Applicant: SILICON GRAPHICS INTERNATIONAL CORP.

Inventor： Randal G. Martin ,  Steven C. Miller ,  Mark D. Stadler ,  David A. Kruckemyer

IPC: H04L12/801 ,  H04L12/825 ,  H04L12/891

CPC classification number: H04L47/34 ,  H04L45/24 ,  H04L47/10 ,  H04L47/26 ,  H04L47/266 ,  H04L47/39 ,  H04L47/41

Abstract: A multiple channel data transfer system (10) includes a source (12) that generates data packets with sequence numbers for transfer over multiple request channels (14). Data packets are transferred over the multiple request channels (14) through a network (16) to a destination (18). The destination (18) re-orders the data packets received over the multiple request channels (14) into a proper sequence in response to the sequence numbers to facilitate data processing. The destination (18) provides appropriate reply packets to the source (12) over multiple response channels (20) to control the flow of data packets from the source (12).

公开(公告)号：US20160337229A1

公开(公告)日：2016-11-17

申请号：US15220189

申请日：2016-07-26

Applicant: SILICON GRAPHICS INTERNATIONAL CORP.

Inventor： Martin M. Deneroff ,  Gregory M. Thorson ,  Randal S. Passint

IPC: H04L12/721 ,  H04L29/08

CPC classification number: G06F15/17312 ,  G06F15/17343 ,  G06F15/17381 ,  H04L45/14 ,  H04L67/1002

Abstract: A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of routers in the scalable interconnect network route messages between the plurality of processing element nodes. One or more metarouters in the scalable interconnect network route messages between the first set of routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters.

公开(公告)号：US09424098B2

公开(公告)日：2016-08-23

申请号：US13931819

申请日：2013-06-29

Applicant: Silicon Graphics International Corp.

Inventor： Eng Lim Goh ,  Christian Tanasescu ,  George L. Thomas ,  Charlton Port

IPC: G06F9/50 ,  G06F11/30 ,  G06F11/07 ,  G06F9/48 ,  G06F1/32 ,  G06N5/00 ,  G06F1/20

CPC classification number: G06F9/5094 ,  G06F1/206 ,  G06F1/3228 ,  G06F1/329 ,  G06F9/4893 ,  G06F9/5083 ,  G06F11/0754 ,  G06F11/3006 ,  G06F11/3058 ,  G06N5/00 ,  Y02D10/16 ,  Y02D10/22 ,  Y02D10/24

Abstract: Embodiments of the invention relate to a system and method for dynamically scheduling resources using policies to self-optimize resource workloads in a data center. The object of the invention is to allocate resources in the data center dynamically corresponding to a set of policies that are configured by an administrator. Operational parametrics that correlate to the cost of ownership of the data center are monitored and compared to the set of policies configured by the administrator. When the operational parametrics approach or exceed levels that correspond to the set of policies, workloads in the data center are adjusted with the goal of minimizing the cost of ownership of the data center. Such parametrics include yet are not limited to those that relate to resiliency, power balancing, power consumption, power management, error rate, maintenance, and performance.

Abstract translation: 本发明的实施例涉及使用策略自动调度资源以自我优化数据中心中的资源工作负载的系统和方法。 本发明的目的是动态地分配数据中心中的资源，与由管理员配置的一组策略相对应。 与数据中心所有权成本相关的操作参数被监控，并与管理员配置的一组策略进行比较。 当操作参数方法或超过对应于一组策略的级别时，调整数据中心的工作负载，以最小化数据中心的所有权成本。 这样的参数包括但不限于与弹性，功率平衡，功耗，功率管理，错误率，维护和性能相关的参数。

公开(公告)号：US09268684B2

公开(公告)日：2016-02-23

申请号：US13931870

申请日：2013-06-29

Applicant: Silicon Graphics International Corp.

Inventor： Steven Dean ,  David R. Collins ,  Paul Kinyon

IPC: G06F13/00 ,  G06F13/28 ,  G06F12/02 ,  G06F3/06 ,  G06F11/20

CPC classification number: G06F12/0246 ,  G06F1/263 ,  G06F3/0635 ,  G06F11/2002 ,  G06F11/2007 ,  G06F11/201 ,  G06F11/2084 ,  G06F11/2089

Abstract: A high performance computing (HPC) system includes computing blades having a first region that includes processors for performing a computation, and a second region that includes non-volatile memory for use in performing the computation and another computing processor for performing data movement and storage. Because data movement and storage are offloaded to the secondary processor, the processors for performing the computation are not interrupted to perform these tasks. A method for use in the HPC system receives instructions in the computing processors and first data in the memory. The method includes receiving second data into the memory while continuing to execute the instructions in the computing processors, without interruption. A computer program product implementing the method is also disclosed.

Abstract translation: 高性能计算（HPC）系统包括具有包括用于执行计算的处理器的第一区域的计算刀片和包括用于执行计算的非易失性存储器的第二区域和用于执行数据移动和存储的另一个计算处理器。 由于数据移动和存储被卸载到次要处理器，所以用于执行计算的处理器不被中断以执行这些任务。 在HPC系统中使用的方法接收计算处理器中的指令和存储器中的第一数据。 该方法包括：在不间断地继续执行计算处理器中的指令的同时，将第二数据接收到存储器中。 还公开了一种实现该方法的计算机程序产品。

公开(公告)号：US09230295B2

公开(公告)日：2016-01-05

申请号：US14303566

申请日：2014-06-12

Applicant: Silicon Graphics International Corp.

Inventor： Phillip C. Keslin

IPC: G06T1/00 ,  G06T15/00 ,  G06T1/20 ,  G06F9/50

CPC classification number: G06T1/20 ,  G06F3/14 ,  G06F9/5044 ,  G06F2209/509 ,  G06T15/005 ,  G06T2200/16 ,  G09G5/36 ,  G09G2370/022 ,  H04L67/42

Abstract: A system, method, and computer program product are provided for remote rendering of computer graphics. The system includes a graphics application program resident at a remote server. The graphics application is invoked by a user or process located at a client. The invoked graphics application proceeds to issue graphics instructions. The graphics instructions are received by a remote rendering control system. Given that the client and server differ with respect to graphics context and image processing capability, the remote rendering control system modifies the graphics instructions in order to accommodate these differences. The modified graphics instructions are sent to graphics rendering resources, which produce one or more rendered images. Data representing the rendered images is written to one or more frame buffers. The remote rendering control system then reads this image data from the frame buffers. The image data is transmitted to the client for display or processing. In an embodiment of the system, the image data is compressed before being transmitted to the client. In such an embodiment, the steps of rendering, compression, and transmission can be performed asynchronously in a pipelined manner.

公开(公告)号：US09229497B2

公开(公告)日：2016-01-05

申请号：US13931730

申请日：2013-06-28

Applicant: Silicon Graphics International Corp.

Inventor： Steven J. Dean ,  Richard B. Salmonson ,  Russell E. Stacy ,  Roger Ramseier ,  Mark Maloney

IPC: H05K5/00 ,  H05K7/00 ,  G06F1/20 ,  H05K7/20 ,  G06F1/18

CPC classification number: G06F1/20 ,  G06F1/181 ,  G06F2200/201 ,  H05K7/20754 ,  H05K7/20827

Abstract: A high performance computing system includes one or more blade enclosures having a cooling manifold and configured to hold a plurality of computing blades, and a plurality of computing blades in each blade enclosure with at least one computing blade including two computing boards. The system further includes two or more cooling plates with each cooling plate between two corresponding computing boards within the computing blade, and a fluid connection coupled to the cooling plate(s) and in fluid communication with the fluid cooling manifold.

Abstract translation: 高性能计算系统包括一个或多个具有冷却歧管并且被配置为保持多个计算刀片的刀片式外壳，以及具有包括两个计算板的至少一个计算刀片的每个刀片机箱中的多个计算刀片。 该系统还包括两个或更多个冷却板，其中每个冷却板位于计算刀片内的两个对应的计算板之间，以及流体连接，其连接到冷却板并与流体冷却歧管流体连通。

公开(公告)号：US09124049B2

公开(公告)日：2015-09-01

申请号：US13853943

申请日：2013-03-29

Applicant: Silicon Graphics International Corp.

Inventor： Peter Siltex Yuen

IPC: H01R24/00 ,  H01R24/60 ,  H01R24/64 ,  H01R13/502 ,  H01R13/66 ,  H01R13/6581 ,  H01R13/6599 ,  H01R12/50 ,  H01R24/68

CPC classification number: H01R24/60 ,  H01R13/502 ,  H01R13/6581 ,  H01R13/6599 ,  H01R13/6658 ,  H01R23/7073 ,  H01R24/64 ,  H01R24/68

Abstract: In an embodiment, a micro ethernet connector includes an outer housing that has a recessed front end and a back end. The micro ethernet connector further includes an inner housing that is disposed within the recessed front end of the outer housing. The inner housing has an exposed end. The exposed end includes a recessed channel. The volume of the recessed channel is substantially equal to the volume of a correspondingly shaped protruding printed circuit board of a male micro ethernet connector. A plurality of spring-biased connectors are disposed within the recessed channel of the inner housing.

Abstract translation: 在一个实施例中，微型以太网连接器包括具有凹入的前端和后端的外壳。 微以太网连接器还包括设置在外壳的凹入前端内的内壳。 内壳具有暴露端。 暴露端包括凹陷通道。 凹槽的体积基本上等于雄性微型以太网连接器的相应形状的突出印刷电路板的体积。 多个弹簧偏置连接器设置在内壳体的凹槽内。

公开(公告)号：US09020897B2

公开(公告)日：2015-04-28

申请号：US14012894

申请日：2013-08-28

Applicant: Silicon Graphics International Corp.

Inventor： Kenneth Beck

IPC: G06F7/00 ,  G06F17/00 ,  G06F17/30 ,  G06F11/20 ,  H04L29/06 ,  H04L29/08

CPC classification number: G06F17/30194 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/067 ,  G06F11/2064 ,  G06F11/2082 ,  G06F17/30067 ,  G06F17/30088 ,  G06F2201/84 ,  H04L29/06 ,  H04L67/10 ,  H04L67/1097 ,  H04L67/2819 ,  H04L67/2833 ,  Y10S707/966

Abstract: A computer system with read/write access to storage devices creates a snapshot of a data volume at a point in time while continuing to accept access requests to the mirrored data volume by copying before making changes to the base data volume. Multiple snapshots may be made of the same data volume at different points in time. Only data that is not stored in a previous snapshot volume or in the base data volume are stored in the most recent snapshot volume.

Abstract translation: 具有对存储设备的读/写访问权限的计算机系统在某个时间点创建数据卷的快照，同时在对基本数据卷进行更改之前，继续通过复制接受对镜像数据卷的访问请求。 可以在不同的时间点对同一数据量做多个快照。 只有不存储在先前快照卷或基本数据卷中的数据才会存储在最新的快照卷中。

公开(公告)号：US08997122B2

公开(公告)日：2015-03-31

申请号：US14492248

申请日：2014-09-22

Applicant: Silicon Graphics International Corp.

Inventor： Peter W. Morreale

IPC: G06F13/00 ,  G06F9/445 ,  G06F13/10

CPC classification number: G06F9/44505 ,  G06F13/10 ,  G06F13/385

Abstract: Embodiments of the present invention perform a method for reading data from, writing data to, powering on, or configuring a block device without the kernel translating a file system operation into a block device operation. This is implemented by a using a core module to couple applications running in user space to a character device through a character device driver, the core module configures the character device to communicate with a block device through a block device driver without the kernel translating a file system command into a block device command.

Abstract translation: 本发明的实施例执行用于从数据读取数据，将数据写入，供电或配置块设备的方法，而不将内核将文件系统操作转换为块设备操作。 这是通过使用核心模块通过字符设备驱动将用户空间中运行的应用程序耦合到字符设备来实现的，核心模块通过块设备驱动器配置字符设备以与块设备通信，而不需要内核翻译文件 系统命令进入块设备命令。

公开(公告)号：US20150074375A1

公开(公告)日：2015-03-12

申请号：US14542023

申请日：2014-11-14

Applicant: Silicon Graphics International Corp.

Inventor： Thomas Edward McGee

IPC: G06F15/78 ,  G06F13/42

CPC classification number: G06F13/4282 ,  G06F13/385 ,  Y02D10/14 ,  Y02D10/151

Abstract: A high performance computing system is provided with an ASIC that communicates with another device in the system according to a protocol defined by the other device. The ASIC is coupled to a reconfigurable protocol table, in the form of a high speed content-addressable memory (“CAM”). The CAM includes instructions to control the execution of the protocol by the ASIC. The CAM may include instructions to control the ASIC in the event that unanticipated signals or other errors are encountered while executing the protocol. Internal ASIC state data may be routed to the CAM to permit the ASIC to generate a reasonable response to errors either in the design or fabrication of the ASIC or the device with which it is communicating.

Abstract translation: 高性能计算系统提供有ASIC，其根据由另一设备定义的协议与系统中的另一设备进行通信。 ASIC以高速内容可寻址存储器（“CAM”）的形式耦合到可重配置协议表。 CAM包括用于控制由ASIC执行协议的指令。 CAM可以包括在执行协议时遇到意外的信号或其他错误的情况下控制ASIC的指令。 内部ASIC状态数据可以路由到CAM，以允许ASIC在ASIC或其正在通信的设备的设计或制造中产生对错误的合理响应。