Determining functional equivalence of configurations of a model

    公开(公告)号:US10275227B1

    公开(公告)日:2019-04-30

    申请号:US14627540

    申请日:2015-02-20

    Abstract: A method may comprise determining, by executing a first model having first configuration parameters, a first result associated with the first model. The method may comprise determining, by executing a second model having second configuration parameters, a second result associated with the second model. The method may comprise determining, based on the first result, the second result, and equivalency criteria, that the second model is not functionally equivalent to the first model. The equivalency criteria may indicate that the second model is functionally equivalent to the first model when a difference between the second result and the first result satisfies a threshold. The method may comprise modifying a configuration parameter, of the second configuration parameters, to cause the second model to improve toward functional equivalence with the first model.

    Automatic replacement of a floating-point function to facilitate fixed-point program code generation

    公开(公告)号:US10168990B1

    公开(公告)日:2019-01-01

    申请号:US14157821

    申请日:2014-01-17

    Abstract: A device may receive a floating-point function. The floating-point function may be a function described in a programming language that uses floating-point representation. The device may determine that fixed-point program code, associated with the floating-point function, is to be generated. The device may determine that the floating-point function is to be replaced with a replacement construct before the fixed-point program code is generated. The replacement construct may be described in the programming language and may be capable of conversion from the floating-point representation to a fixed-point representation. The device may determine parameters associated with generating the replacement construct. The parameters may be determined based on an evaluation of the floating-point function. The device may generate the replacement construct based on the parameters. The device may replace the floating-point function with the replacement construct. The device may generate the fixed-point program code based on the replacement construct.

    SYSTEMS AND METHODS FOR CO-SIMULATION
    125.
    发明申请

    公开(公告)号:US20180349539A1

    公开(公告)日:2018-12-06

    申请号:US15612501

    申请日:2017-06-02

    CPC classification number: G06F17/5009

    Abstract: A model including a first co-simulation component and a second co-simulation component is analyzed. During execution of the model, the first co-simulation component outputs data to the second co-simulation component via a connection. The connection is declared as a continuous-time rate connection for input of the data into the second co-simulation component. Based on analyzing the model, the connection is identified as a discrete-continuous sample time connection based on data being communicated from the first co-simulation component to the second co-simulation component via the connection at a discrete-time rate when the model is executed in a co-simulation manner.

    SYSTEMS AND METHODS FOR RESCALING EXECUTABLE SIMULATION MODELS

    公开(公告)号:US20180347498A1

    公开(公告)日:2018-12-06

    申请号:US15612765

    申请日:2017-06-02

    Inventor: Peter J. Maloney

    Abstract: Systems and methods automatically rescale an original engine model so that it models an engine of a different size. The original engine model may be coupled to an engine controller model, and the systems and methods may also rescale the original controller model to produce a rescaled controller model matched to the rescaled engine model. The original engine model may include engine parameters and engine lookup tables, and the original controller model may include controller parameters and controller lookup tables. Rescaling factors indicating the size of the new engine being modeled may be received, and ratios may be computed as a function of the rescaling factors. Original engine parameters and controller parameters may be rescaled based on the ratios. Original engine lookup tables and controller lookup tables may be reshaped based on the ratios.

    Systems and methods for estimating performance characteristics of hardware implementations of executable models

    公开(公告)号:US10078717B1

    公开(公告)日:2018-09-18

    申请号:US14562647

    申请日:2014-12-05

    Abstract: Systems and methods automatically generate optimized hardware description language code for a model created in a modeling environment. A training tool selects and provides scripts to a hardware synthesis tool chain that direct the tool chain to synthesize hardware components for core components of the modeling environment. A report generated by the tool chain is evaluated to extract performance data for the core components, and the performance data is stored in a library. An optimization tool estimates the performance of the model using the performance data in the library. Based on the performance estimate and an analysis of the model, the optimization tool selects an optimization technique which it applies to the model generating a revised. Estimating performance, and selecting and applying optimizations may be repeated until a performance constraint is satisfied or a termination criterion is met.

    Scheduling technique to transform dataflow graph into efficient schedule

    公开(公告)号:US10025566B1

    公开(公告)日:2018-07-17

    申请号:US15288367

    申请日:2016-10-07

    Abstract: Scheduling techniques transform dataflow graphs (DFGs), for example, of digital signal processing (DSP) arrangements of filters, into efficient schedules for concurrent execution on processing resources coupled to a memory. A DSP arrangement may be represented by an executable model having interconnected filters represented by model elements. The techniques may apply scheduling transforms according to a classification of the model elements based on a lifetime of their internal states (e.g., finite or infinite). Exemplary scheduling transforms may include unfolding, coordinated loop scheduling and pipelining to parallelize a DFG and enhance overall performance, i.e., reduce average sample execution time of the DSP arrangement. Notably, the scheduling transforms may aggregate (i.e., merge) multiple finite state model elements for concurrent execution and repeat execution of infinite state model elements to achieve the overall improved performance.

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