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公开(公告)号：US10078717B1
公开(公告)日：2018-09-18
申请号：US14562647
申请日：2014-12-05
Applicant: The MathWorks, Inc.
Inventor： Girish Venkataramani , Yongfeng Gu , Rama Kokku
IPC: G06F17/50
CPC classification number: G06F17/505 , G06F17/5031 , G06F17/5081 , G06F2217/80 , G06F2217/82 , G06F2217/84
Abstract: Systems and methods automatically generate optimized hardware description language code for a model created in a modeling environment. A training tool selects and provides scripts to a hardware synthesis tool chain that direct the tool chain to synthesize hardware components for core components of the modeling environment. A report generated by the tool chain is evaluated to extract performance data for the core components, and the performance data is stored in a library. An optimization tool estimates the performance of the model using the performance data in the library. Based on the performance estimate and an analysis of the model, the optimization tool selects an optimization technique which it applies to the model generating a revised. Estimating performance, and selecting and applying optimizations may be repeated until a performance constraint is satisfied or a termination criterion is met.
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公开(公告)号：US09846571B1
公开(公告)日：2017-12-19
申请号：US14596443
申请日：2015-01-14
Applicant: The MathWorks, Inc.
Inventor： Girish Venkataramani , Yongfeng Gu , Wang Chen
CPC classification number: G06F8/35 , G06F11/3672
Abstract: A device generates a model associated with a multi-rate system. The multi-rate system includes a system associated with a clock rate and a sample rate, and the clock rate is greater than the sample rate. The device identifies the clock rate of the multi-rate system based on the model, and identifies a portion, of the model, associated with the sample rate. The device applies clock rate pipelining to adjust the sample rate associated with the portion of the model so that the sample rate substantially equals the clock rate, and generates code associated with the model and the applied clock rate pipelining.
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公开(公告)号：US10423733B1
公开(公告)日：2019-09-24
申请号：US15099111
申请日：2016-04-14
Applicant: The Mathworks, Inc.
Inventor： Girish Venkataramani , Yongfeng Gu , Rama Kokku , Sanmukh Rao Kuppannagari
Abstract: A system and method generates optimized code for a source model. The system may include a resource sharing optimizer that evaluates the source model and replaces multiple model elements of the source model that are functionally equivalent with a single shared model element. The model elements replaced with the single shared model element may have different fixed point data types. The resource sharing optimizer may convert some of the fixed point data types to a common fixed point data type.
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公开(公告)号：US08990739B2
公开(公告)日：2015-03-24
申请号：US14096333
申请日：2013-12-04
Applicant: The MathWorks, Inc.
Inventor： Yongfeng Gu , Girish Venkataramani
IPC: G06F17/50
CPC classification number: G06F17/5081 , G06F17/5022 , G06F17/504 , G06F17/505
Abstract: A system and method tests for functional equivalence prior to automatically retiming a high-level specification. An Intermediate Representation (IR) includes one or more graphs or trees based on the high-level specification. A functional equivalence (FE) analyzer determines whether one or more components in the graph meet certain value and state conditions and thus is a candidate for retiming. A bounded scheduler then retimes only those components that pass the FE analysis.
Abstract translation: 在自动重新定义高级规范之前，系统和方法测试功能等效性。 中间表示（IR）包括基于高级规范的一个或多个图或树。 功能等价（FE）分析器确定图中的一个或多个组件是否符合某些值和状态条件，因此是重新定时的候选者。 有限的调度器然后仅重新传递通过FE分析的组件。
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公开(公告)号：US20140157218A1
公开(公告)日：2014-06-05
申请号：US14096333
申请日：2013-12-04
Applicant: The MathWorks, Inc.
Inventor： Yongfeng Gu , Girish Venkataramani
IPC: G06F17/50
CPC classification number: G06F17/5081 , G06F17/5022 , G06F17/504 , G06F17/505
Abstract: A system and method tests for functional equivalence prior to automatically retiming a high-level specification. An Intermediate Representation (IR) includes one or more graphs or trees based on the high-level specification. A functional equivalence (FE) analyzer determines whether one or more components in the graph meet certain value and state conditions and thus is a candidate for retiming. A bounded scheduler then retimes only those components that pass the FE analysis.
Abstract translation: 在自动重新定义高级规范之前，系统和方法测试功能等效性。 中间表示（IR）包括基于高级规范的一个或多个图或树。 功能等价（FE）分析器确定图中的一个或多个组件是否符合某些值和状态条件，因此是重新定时的候选者。 有限的调度器然后仅重新传递通过FE分析的组件。
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Patent Agency Ranking
6.发明申请公开(公告)号：US20200151088A1
公开(公告)日：2020-05-14
申请号：US16270082
申请日：2019-02-07
Applicant: The MathWorks, Inc.
Inventor： Yongfeng Gu , Girish Venkataramani , Wang Chen , Bharathi Yogaraj , Yuteng Zhou , Vibha Patil , Anusha Vasantala , Purshottam Vishwakarma
Abstract: Systems and methods may configure a programmable logic device to efficiently run a deep learning (DL) network. Architecture code and algorithmic code may be generated. The architecture code may define convolutional and fully connected processor cores structured to run the layers of a Deep Neural Network (DNN). The processor cores may be interconnected by a First In First Out (FIFO) memory. The architecture code may also define stride-efficient memories for implementing convolution. The algorithmic code may include configuration instructions for running the DNN's layers at the processor cores. The algorithmic code may also include a schedule for executing the configuration instructions on the processor cores, for moving network parameters to the processor cores, and for transferring outputs between the layers.
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7.发明授权公开(公告)号：US10261760B1
公开(公告)日：2019-04-16
申请号：US14562356
申请日：2014-12-05
Applicant: The Mathworks, Inc.
Inventor： Yongfeng Gu
IPC: G06F8/35
Abstract: Systems and methods trace performance data generated by a hardware synthesis tool chain to model elements of a model. During code generation, an initial in-memory representation is generated for the model. The in-memory representation includes a plurality of nodes that correspond to the model elements. The in-memory representation is subjected to transformations and optimizations creating transitional in-memory representations and a final in-memory representation from which HDL code is generated. A graph builder constructs a genealogy graph that traces the transformations and optimizations. The genealogy graph includes graph objects corresponding to the nodes of the in-memory representations. The synthesis tool chain utilizes the HDL code to perform hardware synthesis. The synthesis tool chain also generates performance data. Utilizing the genealogy graph, the performance data is mapped to the nodes of the initial in-memory representation, and to the elements of the model.
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公开(公告)号：US20150178418A1
公开(公告)日：2015-06-25
申请号：US14640239
申请日：2015-03-06
Applicant: The MathWorks, Inc.
Inventor： Yongfeng Gu , Girish Venkataramani
IPC: G06F17/50
CPC classification number: G06F17/505 , G06F17/5022 , G06F17/504 , G06F17/5081
Abstract: A system and method tests for functional equivalence prior to automatically retiming a high-level specification. An Intermediate Representation (IR) includes one or more graphs or trees based on the high-level specification. A functional equivalence (FE) analyzer determines whether one or more components in the graph meet certain value and state conditions and thus is a candidate for retiming. A scheduler can use components that fail FE as a retiming boundary.
Abstract translation: 在自动重新定义高级规范之前，系统和方法测试功能等效性。 中间表示（IR）包括基于高级规范的一个或多个图或树。 功能等价（FE）分析器确定图中的一个或多个组件是否符合某些值和状态条件，因此是重新定时的候选者。 调度程序可以使用将FE失败的组件作为重定时边界。
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9.发明授权公开(公告)号：US11023360B2
公开(公告)日：2021-06-01
申请号：US16270082
申请日：2019-02-07
Applicant: The MathWorks, Inc.
Inventor： Yongfeng Gu , Girish Venkataramani , Wang Chen , Bharathi Yogaraj , Yuteng Zhou , Vibha Patil , Anusha Vasantala , Purshottam Vishwakarma
Abstract: Systems and methods may configure a programmable logic device to efficiently run a deep learning (DL) network. Architecture code and algorithmic code may be generated. The architecture code may define convolutional and fully connected processor cores structured to run the layers of a Deep Neural Network (DNN). The processor cores may be interconnected by a First In First Out (FIFO) memory. The architecture code may also define stride-efficient memories for implementing convolution. The algorithmic code may include configuration instructions for running the DNN's layers at the processor cores. The algorithmic code may also include a schedule for executing the configuration instructions on the processor cores, for moving network parameters to the processor cores, and for transferring outputs between the layers.
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公开(公告)号：US10095814B1
公开(公告)日：2018-10-09
申请号：US14185514
申请日：2014-02-20
Applicant: The MathWorks, Inc.
Inventor： Partha Biswas , Yongfeng Gu , Zhihong Zhao
IPC: G06F17/50
Abstract: A device is configured to receive delay information associated with a model including a set of model elements and one or more delay elements. The delay information may identify a model element, of the set of model elements, and a quantity of delay to be associated with the model element. The model may be associated with a total quantity of delay. The device is configured to determine accumulated delay information based on the model, and to determine a set of retiming values associated with the set of model elements. The device is configured to redistribute the one or more delay elements associated with the model, based on the set of retiming values, to satisfy the quantity of delay to be associated with the model element, and to maintain the total quantity of delay associated with the model. The device is configured to provide the redistributed model.
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