公开(公告)号：US10984838B2

公开(公告)日：2021-04-20

申请号：US14944099

申请日：2015-11-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S. Jayasena ,  Yasuko Eckert

IPC: G11C5/02 ,  G06F12/0888 ,  G06F12/0811 ,  G06F12/0815 ,  G11C5/06

Abstract: A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions.

公开(公告)号：US10339067B2

公开(公告)日：2019-07-02

申请号：US15626623

申请日：2017-06-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Thiruvengadam Vijayaraghavan ,  Gabriel H. Loh

IPC: G06F12/1036 ,  G06F12/1009

Abstract: A technique for use in a memory system includes swapping a first plurality of pages of a first memory of the memory system with a second plurality of pages of a second memory of the memory system. The first memory has a first latency and the second memory has a second latency. The first latency is less than the second latency. The technique includes updating a page table and triggering a translation lookaside buffer shootdown to associate a virtual address of each of the first plurality of pages with a corresponding physical address in the second memory and to associate a virtual address for each of the second plurality of pages with a corresponding physical address in the first memory.

公开(公告)号：US10303602B2

公开(公告)日：2019-05-28

申请号：US15475435

申请日：2017-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Onur Kayiran ,  Gabriel H. Loh ,  Yasuko Eckert

IPC: G06F12/08 ,  G06F12/0806 ,  G06F12/0804 ,  G06F12/0817

Abstract: A processing system includes at least one central processing unit (CPU) core, at least one graphics processing unit (GPU) core, a main memory, and a coherence directory for maintaining cache coherence. The at least one CPU core receives a CPU cache flush command to flush cache lines stored in cache memory of the at least one CPU core prior to launching a GPU kernel. The coherence directory transfers data associated with a memory access request by the at least one GPU core from the main memory without issuing coherence probes to caches of the at least one CPU core.

公开(公告)号：US10198369B2

公开(公告)日：2019-02-05

申请号：US15469071

申请日：2017-03-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Reena Panda ,  Nuwan Jayasena

IPC: G06F13/16 ,  G06F13/40 ,  G06F3/06

Abstract: A data processing system includes a memory that includes a first memory bank and a second memory bank. The data processing system also includes a conflict detector connected to the memory and adapted to receive memory access information. The conflict detector tracks memory access statistics of the first memory bank, and determines if the first memory bank contains frequent row conflicts. The conflict detector also remaps a frequent row conflict in the first memory bank to the second memory bank. An indirection table is connected to the conflict detector and adapted to receive a memory access request, and redirects an address into a dynamically selected physical memory address in response to a remapping of the frequent row conflict to the second memory bank.

公开(公告)号：US10133678B2

公开(公告)日：2018-11-20

申请号：US14012475

申请日：2013-08-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Syed Ali Jafri ,  Srilatha Manne ,  Gabriel Loh

IPC: G06F12/00 ,  G06F12/126

Abstract: In some embodiments, a method of managing cache memory includes identifying a group of cache lines in a cache memory, based on a correlation between the cache lines. The method also includes tracking evictions of cache lines in the group from the cache memory and, in response to a determination that a criterion regarding eviction of cache lines in the group from the cache memory is satisfied, selecting one or more (e.g., all) remaining cache lines in the group for eviction.

公开(公告)号：US20180276150A1

公开(公告)日：2018-09-27

申请号：US15469071

申请日：2017-03-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Reena Panda ,  Nuwan Jayasena

IPC: G06F13/16 ,  G06F13/40 ,  G06F3/06

CPC classification number: G06F13/1642 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/0673 ,  G06F13/1673 ,  G06F13/4068 ,  Y02D10/14 ,  Y02D10/151

Abstract: A data processing system includes a memory that includes a first memory bank and a second memory bank. The data processing system also includes a conflict detector connected to the memory and adapted to receive memory access information. The conflict detector tracks memory access statistics of the first memory bank, and determines if the first memory bank contains frequent row conflicts. The conflict detector also remaps a frequent row conflict in the first memory bank to the second memory bank. An indirection table is connected to the conflict detector and adapted to receive a memory access request, and redirects an address into a dynamically selected physical memory address in response to a remapping of the frequent row conflict to the second memory bank.

公开(公告)号：US09746908B2

公开(公告)日：2017-08-29

申请号：US14630687

申请日：2015-02-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Derek Hower ,  Marc Orr

IPC: G06F1/32 ,  G06F9/46

CPC classification number: G06F1/3293 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/46 ,  Y02D10/122 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

Abstract: A processor prunes state information based on information provided by software, thereby reducing the amount of state information to be stored prior to the processor entering a low-power state. The software, such as an operating system or application program executing at the processor, indicates one or more registers of the processor as storing data that is no longer useful. When preparing to enter the low-power state, the processor omits the indicated registers from the state information stored to memory.

公开(公告)号：US09734059B2

公开(公告)日：2017-08-15

申请号：US13945659

申请日：2013-07-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Lena E. Olson ,  Yasuko Eckert ,  Vilas K. Sridharan ,  James M. O'Connor ,  Mark D. Hill ,  Srilatha Manne

IPC: G06F12/08 ,  G06F12/0802 ,  G06F12/0875 ,  G06F12/123 ,  G06F12/0846 ,  G06F12/0864 ,  G06F12/0862

CPC classification number: G06F12/0802 ,  G06F12/0848 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/123 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/451 ,  G06F2212/502 ,  G06F2212/601 ,  G06F2212/6032 ,  G06F2212/6082 ,  Y02D10/13

Abstract: A method of way prediction for a data cache having a plurality of ways is provided. Responsive to an instruction to access a stack data block, the method accesses identifying information associated with a plurality of most recently accessed ways of a data cache to determine whether the stack data block resides in one of the plurality of most recently accessed ways of the data cache, wherein the identifying information is accessed from a subset of an array of identifying information corresponding to the plurality of most recently accessed ways; and when the stack data block resides in one of the plurality of most recently accessed ways of the data cache, the method accesses the stack data block from the data cache.

公开(公告)号：US20170083474A1

公开(公告)日：2017-03-23

申请号：US14862011

申请日：2015-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Mitesh R. Meswani ,  David A. Roberts ,  Yasuko Eckert ,  Kapil Dev ,  John Kalamatianos ,  Indrani Paul

IPC: G06F13/42 ,  G06F13/18 ,  G06F12/08

CPC classification number: G06F13/4234 ,  G06F12/084 ,  G06F12/0862 ,  G06F13/18 ,  G06F2212/314 ,  G06F2212/603 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A plurality of first controllers operate according to a plurality of access protocols to control a plurality of memory modules. A second controller receives access requests that target the plurality of memory modules and selectively provides the access requests and control information to the plurality of first controllers based on physical addresses in the access requests. The second controller generates the control information for the first controllers based on statistical representations of the access requests to the plurality of memory modules.

公开(公告)号：US20170083444A1

公开(公告)日：2017-03-23

申请号：US14862030

申请日：2015-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Kapil Dev ,  Mitesh R. Meswani ,  David A. Roberts ,  Yasuko Eckert ,  Indrani Paul ,  John Kalamatianos

IPC: G06F12/08 ,  G06F12/10 ,  G06F12/12

CPC classification number: G06F12/0871 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/121 ,  G06F2212/1024 ,  G06F2212/214 ,  G06F2212/2515 ,  G06F2212/502 ,  G06F2212/601

Abstract: A cache controller to configure a portion of a first memory as cache for a second memory responsive to an indicator of locality of memory access requests to the second memory. The indicator of locality determines a probability that a location of a memory access request to the second memory is predictable based upon at least one previous memory access request. The cache controller may determine a size of the cache based on a value of the indicator of locality or modify the size of the cache in response to changes in the value of the indicator of locality.