公开(公告)号：US11284518B1

公开(公告)日：2022-03-22

申请号：US17089748

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Jenny Shio Yin Ong ,  Seok Ling Lim

IPC: H05K1/16 ,  H05K3/34 ,  H05K1/18

Abstract: According to various examples, a device is described. The device may include a printed circuit board. The device may also include a first recess in the printed circuit board, wherein the first recess comprises a circular side surface and a bottom surface. The device may also include a first solder ball disposed in the first recess. The device may also include a first conductive wall positioned behind the circular side surface of the first recess, wherein the first conductive wall surrounds a side surface of the first solder ball.

公开(公告)号：US20210384133A1

公开(公告)日：2021-12-09

申请号：US16987437

申请日：2020-08-07

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Saravanan Sethuraman

IPC: H01L23/538 ,  H01L23/552 ,  H01L23/498 ,  H01L21/48

Abstract: Semiconductor packages, and methods for making the semiconductor packages, having an interposer structure with one or more interposer and an extension platform, which has an opening for placing the interposer, and the space between the interposer and the extension platform is filled with a polymeric material to form a unitary interposer-extension platform composite structure. A stacked structure may be formed by at least a first semiconductor chip coupled to the interposer and at least a second semiconductor chip coupled to the extension platform, and at least one bridge extending over the space that electrically couples the extension platform and the interposer. The extension platform may include a recess step section that may accommodate a plurality of passive devices to reduced power delivery inductance loop for the high-density 2.5D and 3D stacked packaging applications.

公开(公告)号：US11121074B2

公开(公告)日：2021-09-14

申请号：US16819963

申请日：2020-03-16

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Mooi Ling Chang ,  Ping Ping Ooi ,  Jackson Chung Peng Kong ,  Wen Wei Lum

IPC: H01L23/522 ,  H01L49/02 ,  H01L25/16 ,  H01L23/00 ,  H01G4/30 ,  H01L25/065 ,  H01G4/40 ,  H01G4/38 ,  H01L23/538 ,  H01L23/50

Abstract: A stacked-die and stacked-capacitor package vertically arranged capacitors to mirror a semiconductive-device stack. The stacked capacitor can be electrically coupled to one or more semiconductive devices in the stacked architecture.

公开(公告)号：US11049801B2

公开(公告)日：2021-06-29

申请号：US16279656

申请日：2019-02-19

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi ,  Yang Liang Poh

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package substrate includes an encapsulated interconnect on a land side of the substrate. The encapsulated interconnect includes an integral metallic structure that has a smaller contact end against the semiconductor package substrate, and a larger contact end for board mounting.

公开(公告)号：US10980108B2

公开(公告)日：2021-04-13

申请号：US16469105

申请日：2017-11-22

Applicant: Intel Corporation

Inventor： Ping Ping Ooi ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi

IPC: H05K1/02 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

Abstract: A multi-conductor interconnect for a microelectronic device incorporates multiple conductors and integrated shielding for the conductors. The multi-conductor interconnect includes first and second groups of conductors interleaved with one another within a dielectric structure. One of the groups of conductors may be coupled to a reference voltage node to provide shielding for the other group of conductors. The multi-conductor interconnect may further include a shield layer extending over some portion, or all, of the conductors of the first and second groups.

公开(公告)号：US10973116B2

公开(公告)日：2021-04-06

申请号：US16328535

申请日：2017-08-29

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Khang Choong Yong ,  Ramaswamy Parthasarathy

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/10 ,  H05K3/46 ,  H01P3/00 ,  H01P3/08 ,  H03H7/38 ,  H03H7/42

Abstract: Embodiments are generally directed to 3D high-inductive ground plane for crosstalk reduction. An embodiment of a printed circuit board includes a first signal trace and a second signal trace on a first layer, wherein the first signal trace and second signal trace are non-intersecting; a second layer below the first layer; a third layer below the second layer; and a three-dimensional (3D) ground plane, the 3D ground plane including a first plurality of segments on the third layer, a second plurality of segments on the second layer, and a plurality of metal vias to connect the first plurality of segments and the second plurality of segments in the ground plane.

公开(公告)号：US10964677B2

公开(公告)日：2021-03-30

申请号：US15845492

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Seok Ling Lim ,  Kooi Chi Ooi

IPC: H01L25/00 ,  H01L25/16 ,  H01L21/48 ,  H01L23/00 ,  H01L23/492 ,  H01L23/538 ,  H01L23/367 ,  H01L23/13 ,  H01L23/16 ,  H01L23/50 ,  H01L23/36 ,  H01L23/498 ,  H05K1/18

Abstract: A semiconductor package apparatus includes a passive device that is embedded in a bottom package stiffener, and a top stiffener is stacked above the bottom package stiffener. Electrical connection through the passive device is accomplished through the stiffeners to a semiconductor die that is seated upon an infield region of the semiconductor package substrate.

公开(公告)号：US10950552B2

公开(公告)日：2021-03-16

申请号：US16401661

申请日：2019-05-02

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Kooi Chi Ooi ,  Paik Wen Ong

IPC: H01L21/00 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L25/18 ,  H01L25/16 ,  H01L23/498 ,  H01L23/50 ,  H05K3/34 ,  H05K1/18 ,  H01L25/00 ,  H01L23/64 ,  H01L25/065

Abstract: Ring-in-ring stiffeners on a semiconductor package substrate includes a passive device that is seated across the ring stiffeners. The ring-in-ring stiffeners are also electrically coupled to traces in the semiconductor package substrate through electrically conductive adhesive that bonds a given ring stiffener to the semiconductor package substrate. The passive device is embedded between the two ring stiffeners to create a smaller X-Y footprint as well as a lower Z-direction profile.

公开(公告)号：US20210051801A1

公开(公告)日：2021-02-18

申请号：US16887902

申请日：2020-05-29

Applicant: Intel Corporation

Inventor： Tin Poay Chuah ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H05K1/14 ,  H01R12/77 ,  H05K1/02 ,  H05K1/18 ,  H05K3/30 ,  H05K3/36

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a first rigid substrate, a second rigid substrate, a flexible substrate comprising a first portion attached to the first rigid substrate, a second portion attached to the second rigid substrate, a middle portion connecting the first portion to the second portion, wherein the middle portion is bent, and metallic traces therethrough, and a component forming a direct interface with the middle portion of the flexible substrate, the component electrically coupled to the metallic traces. In selected examples, the device further includes a casing.

公开(公告)号：US10903155B2

公开(公告)日：2021-01-26

申请号：US16402553

申请日：2019-05-03

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong ,  Seok Ling Lim

IPC: H01L23/498 ,  H01L23/66 ,  H01L23/552 ,  H01L23/00 ,  H01L25/18

Abstract: Disclosed embodiments include a stacked multi-chip package that includes two semiconductor package substrates that are spaced apart by a vertical-device stiffener. The vertical-device stiffener provides both connection space for at least one vertical semiconductive device and at least one vertical radio-frequency device, as well as stiffness and form-factor reduction.