公开(公告)号：US20230006060A1

公开(公告)日：2023-01-05

申请号：US17682370

申请日：2022-02-28

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Narayana Sateesh Pillai ,  Gangqiang Zhang ,  Angelo William Pereira

IPC: H01L29/78 ,  H01L29/66

Abstract: An integrated circuit includes a first field effect transistor (FET) and a second FET formed in or over a semiconductor substrate and configured to selectively conduct a current between a first circuit node and a second circuit node. The first FET has a first source, a first drain and a first buried layer all having a first conductivity type, and a first gate between the first source and the first drain. The second FET has a second source, a second drain and a second buried layer all having the first conductivity type, and a second gate between the second source and the second drain. A first potential between the first source and the first buried layer is configurable independently from a second potential between the second source and the second buried layer.

公开(公告)号：US20220271158A1

公开(公告)日：2022-08-25

申请号：US17487149

申请日：2021-09-28

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  Henry Litzmann Edwards ,  Curry Bachman Taylor

IPC: H01L29/78 ,  H01L29/40

Abstract: A microelectronic device includes a hybrid component. The microelectronic device has a substrate including silicon semiconductor material. The hybrid component includes a silicon portion in the silicon, and a wide bandgap (WBG) structure on the silicon. The WBG structure includes a WBG semiconductor material having a bandgap energy greater than a bandgap energy of the silicon. The hybrid component has a first current terminal on the silicon, and a second current terminal on the WBG semiconductor structure. The microelectronic device may be formed by forming the silicon portion of the hybrid component in the silicon, and subsequently forming the WBG structure on the silicon.

公开(公告)号：US20220271128A1

公开(公告)日：2022-08-25

申请号：US17487187

申请日：2021-09-28

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  Henry Litzmann Edwards ,  Curry Bachman Taylor

IPC: H01L29/267 ,  H01L29/165 ,  H01L21/02 ,  H01L29/78 ,  H01L29/40

Abstract: A microelectronic device includes a hybrid component. The microelectronic device has a substrate including silicon semiconductor material. The hybrid component includes a silicon portion in the silicon, and a wide bandgap (WBG) structure on the silicon. The WBG structure includes a WBG semiconductor material having a bandgap energy greater than a bandgap energy of the silicon. The hybrid component has a first current terminal on the silicon, and a second current terminal on the WBG structure. The microelectronic device may be formed by forming the silicon portion of the hybrid component in the silicon, and subsequently forming the WBG structure in a silicon recess on the silicon.

公开(公告)号：US11085961B2

公开(公告)日：2021-08-10

申请号：US16226318

申请日：2018-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Robert Allan Neidorff ,  Henry Litzmann Edwards

IPC: G01R31/26 ,  G01R31/30 ,  G01R19/00 ,  G01R19/165 ,  G01R31/50

Abstract: An example method provides a power MOSFET, a voltage source coupled to the power MOSFET, and a current measurement device coupled to a first non-control terminal of the power MOSFET. The voltage source, the current measurement device, and a second non-control terminal of the power MOSFET couple to ground. The method uses the voltage source to apply a voltage between a gate terminal and the second non-control terminal of the power MOSFET, the voltage greater than zero volts and less than a threshold voltage of the power MOSFET. The method also uses the current measurement device to measure a first current flowing through the first non-control terminal while applying the voltage. The method further uses the first current to predict a second current through the first non-control terminal for a voltage between the gate terminal and the second non-control terminal that is approximately zero.

公开(公告)号：US10861948B2

公开(公告)日：2020-12-08

申请号：US16683517

申请日：2019-11-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann Edwards ,  Binghua Hu ,  James Robert Todd

IPC: H01L29/40 ,  H01L29/78 ,  H01L21/32 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L21/266 ,  H01L27/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/265 ,  H01L21/324 ,  H01L21/762 ,  H01L29/06 ,  H01L29/167 ,  H01L21/225

Abstract: An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region. Dopants are implanted into the substrate under the first opening. Subsequently, dielectric sidewalls are formed along a lateral boundary of the first opening. A field relief oxide is formed by thermal oxidation in the area of the first opening exposed by the dielectric sidewalls. The implanted dopants are diffused into the substrate to form the drift region, extending laterally past the layer of field relief oxide. The dielectric sidewalls and layer of oxide mask are removed after the layer of field relief oxide is formed. A gate is formed over a body of the field-plated FET and over the adjacent drift region. A field plate is formed immediately over the field relief oxide adjacent to the gate.

公开(公告)号：US10784251B2

公开(公告)日：2020-09-22

申请号：US16371960

申请日：2019-04-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann Edwards ,  Akram Ali Salman

IPC: H01L27/02 ,  H01L23/528 ,  H01L29/66 ,  H01L21/8249 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/732 ,  H01L27/082 ,  H01L29/417 ,  H01L29/78

Abstract: An integrated circuit includes a plurality of first n-type regions and a plurality of second n-type regions that each intersect a surface of a substrate. The first n-type regions are arranged in a first linear array within a first n-well and a second linear array within a second n-well. The first and second n-wells are each located within and separated by a first p-type region. The second n-type regions are located within and separated by a second p-type region. An n-type trench region is located between the first and second p-type regions. The n-type trench region extends into the substrate toward an n-type buried layer that extends under the first p-type region and the second p-type region.

公开(公告)号：US10714594B2

公开(公告)日：2020-07-14

申请号：US15813934

申请日：2017-11-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann Edwards ,  Andrew D. Strachan

IPC: H01L29/66 ,  H01L21/266 ,  H01L29/06 ,  H01L21/762 ,  H01L29/10 ,  H01L29/78 ,  H01L29/40

Abstract: A method to fabricate a transistor includes implanting dopants into a semiconductor to form a drift layer having majority carriers of a first type; etching a trench into the semiconductor; thermally growing an oxide liner into and on the trench and the drift layer; depositing an oxide onto the oxide liner on the trench to form a shallow trench isolation region; implanting dopants into the semiconductor to form a drain region in contact with the drift layer and having majority carriers of the first type; implanting dopants into the semiconductor to form a body region having majority carriers of a second type; forming a gate oxide over a portion of the drift layer and the body region; forming a gate over the gate oxide; and implanting dopants into the body region to form a source region having majority carriers of the first type.

公开(公告)号：US10707296B2

公开(公告)日：2020-07-07

申请号：US16156827

申请日：2018-10-10

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards

IPC: H01L21/762 ,  H01L29/94 ,  H01L29/92 ,  H01L21/311 ,  H01L21/3205 ,  H01L49/02

Abstract: An integrated circuit (IC) includes a first capacitor, a second capacitor, and functional circuitry configured together with the capacitors for realizing at least one circuit function in a semiconductor surface layer on a substrate. The capacitors include a top plate over a LOCal Oxidation of Silicon (LOCOS) oxide, wherein a thickness of the LOCOS oxide for the second capacitor is thicker than a thickness of the LOCOS oxide for the first capacitor. There is a contact for the top plate and a contact for a bottom plate for the first and second capacitors.

公开(公告)号：US20200161471A1

公开(公告)日：2020-05-21

申请号：US16750020

申请日：2020-01-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Xiaoju Wu ,  Robert James Todd ,  Henry Litzmann Edwards

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/285 ,  H01L21/225 ,  H01L21/324 ,  H01L21/265 ,  H01L21/762 ,  H01L21/74 ,  H01L29/10 ,  H01L29/40 ,  H01L29/06

Abstract: A semiconductor device includes a local oxidation of silicon (LOCOS) structure and a shallow trench isolation (STI) structure formed over a semiconductor substrate. A source region is located between the LOCOS structure and the STI structure. A gate structure is located between the source region and the LOCOS structure. A contact may be located over the STI structure electrically connect to the gate structure.

公开(公告)号：US20200083336A1

公开(公告)日：2020-03-12

申请号：US16683517

申请日：2019-11-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann Edwards ,  Binghua Hu ,  James Robert Todd

IPC: H01L29/40 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/167 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L27/088 ,  H01L27/06 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/324 ,  H01L21/32 ,  H01L21/265 ,  H01L21/266 ,  H01L21/225

Abstract: An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region. Dopants are implanted into the substrate under the first opening. Subsequently, dielectric sidewalls are formed along a lateral boundary of the first opening. A field relief oxide is formed by thermal oxidation in the area of the first opening exposed by the dielectric sidewalls. The implanted dopants are diffused into the substrate to form the drift region, extending laterally past the layer of field relief oxide. The dielectric sidewalls and layer of oxide mask are removed after the layer of field relief oxide is formed. A gate is formed over a body of the field-plated FET and over the adjacent drift region. A field plate is formed immediately over the field relief oxide adjacent to the gate.