公开(公告)号：US5778419A

公开(公告)日：1998-07-07

申请号：US606342

申请日：1996-02-23

Applicant: Craig C. Hansen ,  Timothy B. Robinson ,  Alan G. Corry

Inventor： Craig C. Hansen ,  Timothy B. Robinson ,  Alan G. Corry

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/308 ,  G06F9/312 ,  G06F9/315 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10 ,  G06F15/78 ,  H04N5/00 ,  H04N7/24 ,  G06F12/00

CPC classification number: G06F9/3802 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3869 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  G06F2212/2515 ,  Y02B60/1225

Abstract: A memory chip for storage and retrieval of data transmitted as streams of data at sustained peak data transfer rates. The memory chip includes a memory device and an interface capable of achieving high bandwidth throughput. The memory device decodes, arbitrates between, and executes memory access commands, and generates memory access responses. The interface includes a data path, and a number of memory controllers. The interface receives and transmits input and output data streams, and the memory controllers control the flow of the input and output data streams within the memory chip. A packet buffer is coupled between the data path and the memory device. The packet buffer provides for temporary storage of memory access commands, response information, and forwarding data.

Abstract translation: 一种存储芯片，用于存储和检索以持续的峰值数据传输速率传输的数据流。 存储器芯片包括能够实现高带宽吞吐量的存储器件和接口。 存储器件解码，仲裁并执行存储器访问命令，并产生存储器访问响应。 该接口包括数据路径和多个存储器控制器。 该接口接收和发送输入和输出数据流，并且存储器控制器控制存储器芯片内的输入和输出数据流的流动。 分组缓冲器耦合在数据路径和存储器件之间。 分组缓冲区提供临时存储内存访问命令，响应信息和转发数据。

公开(公告)号：US5742840A

公开(公告)日：1998-04-21

申请号：US516036

申请日：1995-08-16

Applicant: Craig Hansen ,  John Moussouris

Inventor： Craig Hansen ,  John Moussouris

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/308 ,  G06F9/312 ,  G06F9/315 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10 ,  G06F15/78 ,  H04N5/00 ,  H04N7/24 ,  G06F7/38

CPC classification number: G06F9/3802 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3869 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  G06F2212/2515 ,  Y02B60/1225

Abstract: A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor. The general purpose, programmable media processor is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams. Parallel general purpose media processors are disposed throughout the network in a distributed virtual manner to allow for multi-processor operations and sharing of resources through the network. A method for receiving, processing and transmitting media data streams over the communications fabric is also provided.

Abstract translation: 一种通用的可编程媒体处理器，用于实时处理和传输音频，视频，无线电，图形，加密，认证和网络信息的媒体数据流。 媒体处理器包含执行单元，其在整个媒体数据流中保持基本的峰值数据。 执行单元包括动态分立的多精度算术单元，可编程开关和可编程扩展数学元素。 高带宽外部接口以基本上峰值的速率将媒体数据流提供给通用寄存器文件和多精度执行单元。 还提供了存储器管理单元以及指令和数据高速缓冲存储器/缓冲器。 高带宽存储器控制器串联连接，为通用的可编程媒体处理器提供存储通道。 通用的可编程媒体处理器被布置在由光纤电缆，同轴电缆和双绞线组成的网络结构中，以传输，处理和接收单个或统一的媒体数据流。 平行通用媒体处理器以分布式虚拟方式在整个网络中进行布置，以允许通过网络进行多处理器操作和资源共享。 还提供了一种用于通过通信结构接收，处理和传送媒体数据流的方法。

公开(公告)号：US5519338A

公开(公告)日：1996-05-21

申请号：US305650

申请日：1994-09-14

Applicant: John G. Campbell ,  Ban P. Wong

Inventor： John G. Campbell ,  Ban P. Wong

IPC: H03K19/003 ,  H03K19/013 ,  H03K19/0175 ,  H03K19/02 ,  H03K17/16

CPC classification number: H03K19/0136 ,  H03K19/00353 ,  H03K19/017581

Abstract: An output buffer that controls the slew rate of its output signal is disclosed. The buffer includes a pull-up and a pull-down bipolar transistor coupled at a common output node in series between VDD and VSS. The buffer also includes a first set of parallel MOS devices coupled between the common output node and the base of the pull-down bipolar transistor. A second set of parallel MOS devices are coupled between the base of the pull-up output stage bipolar transistor and VDD. The gates of each set of MOS devices are coupled to a digital select signal. The amount of current driving the base of each of the pull-up and pull-down transistors (when they are enabled) is determined by the number of MOS devices enabled by the digital select signal. Thus, the buffer of the present invention is able to adjust the slew rate of its output signal to accommodate different loads coupled to the common output node.

Abstract translation: 公开了一种控制其输出信号的转换速率的输出缓冲器。 该缓冲器包括耦合在VDD和VSS之间串联的公共输出节点的上拉和下拉双极晶体管。 缓冲器还包括耦合在公共输出节点和下拉双极晶体管的基极之间的第一组并联MOS器件。 第二组并联MOS器件耦合在上拉输出级双极晶体管的基极和VDD之间。 每组MOS器件的栅极耦合到数字选择信号。 每个上拉和下拉晶体管（当它们被使能时）驱动基极的电流量由数字选择信号使能的MOS器件的数量决定。 因此，本发明的缓冲器能够调节其输出信号的转换速率以适应耦合到公共输出节点的不同负载。

公开(公告)号：US5506541A

公开(公告)日：1996-04-09

申请号：US416531

申请日：1995-04-03

Applicant: William H. Herndon

Inventor： William H. Herndon

IPC: G05F3/24 ,  H03K19/00 ,  H03K19/086 ,  G05F1/10

CPC classification number: G05F3/24

Abstract: A bias generation and distribution system in which bias potentials are generated at one main location within a logic circuit and then distributed throughout the logic circuit to MOS load devices, MOS load networks, other bias voltage conversion centers, and logic circuits is disclosed. The system generates a first bias voltage that provides a temperature compensated voltage that is utilized to bias MOS load devices and parallel MOS load networks. The first bias voltage generator includes either a reference MOS load device or a reference parallel MOS load network which determines the value of the first bias voltage. The reference MOS load network includes a switching network responsive to a first set of control signals. The first set of control signals may be adjusted to vary the value of the first bias voltage to compensate for process variations. The first bias voltage is distributed to either remote single load MOS devices or to remote parallel MOS load networks. The remote load networks also include switching networks responsive to a second set of control signals. The second set of control signals may be varied to determine the resistivity of the remote MOS load networks depending on the value of the first bias voltage. The system also generates a second temperature compensated bias voltage that is utilized along with the first bias voltage to bias remote bias conversion circuits. The remote conversion circuits generate a third bias voltage that is utilized, along with the first bias voltage, to bias remote logic gates. The first bias voltage biases the MOS resistive load of the logic gate and the third bias voltage biases the MOS current device of the logic gate. The second bias voltage generator and the remote conversion circuits are implemented with controllable switching networks so that current and logic swing adjustments of the logic gate may be performed.

Abstract translation: 一种偏置发生和分配系统，其中在逻辑电路内的一个主要位置处产生偏置电位，然后在整个逻辑电路中分配到MOS负载器件，MOS负载网络，其他偏置电压转换中心和逻辑电路。 该系统产生第一偏置电压，其提供用于偏置MOS负载装置和并联MOS负载网络的温度补偿电压。 第一偏置电压发生器包括参考MOS负载装置或参考并联MOS负载网络，其确定第一偏置电压的值。 参考MOS负载网络包括响应于第一组控制信号的交换网络。 可以调整第一组控制信号以改变第一偏置电压的值以补偿过程变化。 第一个偏置电压分配到远程单负载MOS器件或远程并行MOS负载网络。 远程负载网络​​还包括响应于第二组控制信号的交换网络。 可以改变第二组控制信号以根据第一偏置电压的值确定远程MOS负载网络的电阻率。 该系统还产生第二温度补偿偏置电压，其与第一偏置电压一起使用以偏置远程偏置转换电路。 远程转换电路产生与第一偏置电压一起被利用以偏置远程逻辑门的第三偏置电压。 第一偏置电压偏置逻辑门的MOS电阻负载，第三偏置电压偏置逻辑门的MOS电流器件。 第二偏置电压发生器和远程转换电路由可控开关网络实现，从而可以执行逻辑门的电流和逻辑摆幅调整。

公开(公告)号：US5242770A

公开(公告)日：1993-09-07

申请号：US821793

申请日：1992-01-16

Applicant: Jang F. Chen ,  James A. Matthews

Inventor： Jang F. Chen ,  James A. Matthews

IPC: G03F1/00 ,  G03F1/36 ,  G03F7/20 ,  G03F9/00 ,  H01L21/027

CPC classification number: G03F1/36 ,  G03F7/70433 ,  G03F7/70441

Abstract: An improvement for reducing proximity effects comprised of additional lines, referred to as intensity leveling bars, into the mask pattern. The leveling bars perform the function of adjusting the edge intensity gradients of isolated edges in the mask pattern, to match the edge intensity gradients of densely packed edges. Leveling bars are placed parallel to isolated edges such that intensity gradient leveling occurs on all isolated edges of the mask pattern. In addition, the leveling bars are designed to have a width significantly less than the resolution of the exposure tool. Therefore, leveling bars that are present in the mask pattern produce resist patterns that completely developed away when a nominal exposure energy is utilized during exposure of photoresist.

Abstract translation: 用于减少由附加线（称为强度调平条）组成的接近效应进入掩模图案的改进。 调平条执行调整掩模图案中孤立边缘的边缘强度梯度的功能，以匹配密集边缘的边缘强度梯度。 调平条平行于孤立的边缘放置，使得强度梯度平整发生在掩模图案的所有隔离边缘上。 此外，调平条被设计成具有明显小于曝光工具的分辨率的宽度。 因此，当在光致抗蚀剂的曝光期间使用标称曝光能量时，存在于掩模图案中的调平条产生完全展开的抗蚀剂图案。

公开(公告)号：US5134083A

公开(公告)日：1992-07-28

申请号：US647707

申请日：1991-01-28

Applicant: James A. Matthews

Inventor： James A. Matthews

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/417

CPC classification number: H01L21/28211 ,  H01L21/28525 ,  H01L21/7688 ,  H01L21/76897 ,  H01L21/8249 ,  H01L29/41708 ,  H01L29/41775 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S148/136

Abstract: A method for forming a BICMOS integrated circuit having MOS field-effect devices and bipolar junction transistors formed in a silicon substrate is disclosed. The process comprises the steps of first defining separate active areas in a substrate for each of the transistors. Next, a gate dielectric layer is formed over the surface of the wafer. Above the gate dielectric, a first layer of polysilicon is deposited. This first layer of polysilicon is then selectively etched to form a plurality of first polysilicon members each of which is equally-spaced apart from one another. The polysilicon members comprise the gates of the MOS transistors and the extrinsic base contacts of the NPN transistors. After the first polysilicon members have been defined, the base regions of the NPN transistors are formed. After insulating the first polysilicon members, an additional layer of polysilicon is deposited over the substrate to replanarize the entire wafer surface. The additional layer of polysilicon is then etched to form a plurality of second polysilicon members which are electrically isolated from the first polysilicon members. Impurities are diffused from the polysilicon members into the substrate to form the source/drain regions of the MOS transistors, and the extrinsic base and emitter regions of the NPN transistors. The final processing steps include those required to the interconnection of the MOS and NPN transistors. Self-aligned interconnects are formed by patterning polysilicon, an insulative layer, And a silicide layer, using first silicide contacts over device components as etch stop.

公开(公告)号：US5107460A

公开(公告)日：1992-04-21

申请号：US535728

申请日：1990-06-11

Applicant: James A. Matthews

Inventor： James A. Matthews

IPC: G02F1/09 ,  G02F1/19 ,  G11B11/00 ,  G11B11/10 ,  G11B11/105 ,  G11C7/00 ,  G11C11/18 ,  G11C13/04 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  H01L43/06 ,  H01S3/10

CPC classification number: G11C11/18 ,  G02F1/09 ,  G02F1/19 ,  G11C13/04 ,  G11C7/005

Abstract: An optical modulator utilizing a magnetic semiconductor device, whose operation is based on the Hall effect, includes a magnetic material formed on a semiconductor substrate. When an incoming beam of light having a dominant polarization direction is directed onto the magnetic material it becomes modulated. The result is an outgoing beam of light which has a rotated plane of polarization when compared to the dominant polarization direction. The direction of the rotated plane of polarization is indicative of the information stored in the magnetic material. The modulator of the present invention further includes a means for writing the information to the magnetic material and a semiconductor sensor means for electrically verifying the contents of the magnetic material.

Abstract translation: 利用基于霍尔效应的操作的磁性半导体器件的光调制器包括形成在半导体衬底上的磁性材料。 当具有主偏振方向的入射光束被引导到磁性材料上时，其被调制。 结果是与主偏振方向相比，具有旋转的偏振平面的输出光束。 旋转的偏振平面的方向表示存储在磁性材料中的信息。 本发明的调制器还包括用于将信息写入磁性材料的装置和用于电验证磁性材料的内容物的半导体传感器装置。