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公开(公告)号：US10700901B1
公开(公告)日：2020-06-30
申请号：US16587248
申请日：2019-09-30
Applicant: Silicon Laboratories Inc.
Inventor： Antonio Torrini , Joel Kauppo , Sauli Johannes Lehtimaki
Abstract: A system and method for detecting and compensating for carrier frequency offset is disclosed. This system compensates for CFO and calculates a corrected phase. This corrected phase may be used by, for example, an AoX algorithm, such as MUSIC, to more accurately determine the angle of arrival or angle of departure of a signal. In certain embodiments, the system oversamples the incoming signal to create a plurality of samples. The system then determines the phase of each of the plurality of samples and calculates the carrier frequency based on the time derivative of the phase. In certain embodiments, a particular portion of an incoming packet is used to determine the carrier frequency offset. In other embodiments, the system calculates the carrier frequency offset throughout an entirety of the incoming packet. Once the carrier frequency offset is determined, it can be used to adjust the received signals. These adjusted signals are then used to determine the angle of arrival or angle of departure.
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公开(公告)号：US10699995B2
公开(公告)日：2020-06-30
申请号：US15974857
申请日：2018-05-09
Applicant: Silicon Laboratories Inc.
Inventor： Michael R. May , Charles Guo Lin , Carlos Briseno-Vidrios
IPC: H01L23/498 , H01L23/00 , H01L23/64
Abstract: An integrated circuit isolation product includes a first integrated circuit die. The first integrated circuit die includes a first terminal and a second terminal adjacent to the first terminal. The first terminal and the second terminal are configured as a differential pair of terminals configured to communicate a differential signal across an isolation barrier. The first integrated circuit die includes at least one additional terminal adjacent to the differential pair of terminals. The at least one additional terminal is disposed symmetrically with respect to the differential pair of terminals. The first terminal may have a first parasitic capacitance and the second terminal may have a second parasitic capacitance. The first parasitic capacitance may be substantially the same as the second parasitic capacitance. The at least one additional terminal may be disposed symmetrically with respect to a line of symmetry for the differential pair of terminals.
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公开(公告)号：US10693475B1
公开(公告)日：2020-06-23
申请号：US16427837
申请日：2019-05-31
Applicant: Silicon Laboratories Inc.
Inventor： Xue-Mei Gong , James D. Barnette
IPC: H03L7/093
Abstract: A method for generating a clock signal by a phase-locked loop includes generating a phase difference signal based on an input clock signal and a feedback clock signal and generating a loop filter output signal. In a first mode, the loop filter output signal is generated based on the phase difference signal and a predetermined frequency slope, and may include generating a phase-slope-limited version of the phase difference signal based on a predetermined phase slope limit and generating a frequency-slope-limited version of the phase difference signal based on the predetermined frequency slope limit. In a second mode, the loop filter output signal may be generated based on the predetermined frequency slope limit, a value of the loop filter output signal, and a target frequency. In the second mode, the loop filter output signal may be generated further based on a predetermined frequency step value.
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公开(公告)号：US10678674B2
公开(公告)日：2020-06-09
申请号：US15623761
申请日：2017-06-15
Applicant: Silicon Laboratories Inc.
Inventor： Lauri Mikael Hintsala
Abstract: A novel system and method for remotely debugging a network device is disclosed. A debug system is used to transmit debug commands over a network to the network device. The network device interprets the debug commands. The processing unit on the network device includes a special debugging mode where it is able to perform special debug operations. This special debugging mode operates at a priority that is lower than that of the network interface so that the network device can still receive network packets while being debugged. The network device also has the ability to generate responses to the debug commands in some embodiments. The concept of wireless debugging can also be applied to multi-core processors as well.
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公开(公告)号：US10673688B2
公开(公告)日：2020-06-02
申请号：US16137815
申请日：2018-09-21
Applicant: Silicon Laboratories Inc.
Inventor： Christian Salmony Olsen , Jørgen Franck , Peter Shorty , Anders T. Brandt
Abstract: A system and method for improving network resiliency is disclosed. The system includes a network having a plurality of network devices and at least one controller. The controller is configured to create various scenes based on the inputs received from the network devices. The controller is also configured to provide alternate instructions to the network devices in the event that the controller is non-functional. The network devices utilize these alternate instructions when attempts to connect the controller are unsuccessful. In this way, the network is able to operate in a limited way even in the absence of the controller.
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Patent Agency Ranking
公开(公告)号：US20200162079A1
公开(公告)日：2020-05-21
申请号：US16661049
申请日：2019-10-23
Applicant: Silicon Laboratories Inc.
Inventor： Aaron J. Caffee , Brian G. Drost
Abstract: A method for reducing deterministic jitter in a clock generator includes providing a load current through a regulated voltage node to a circuit responsive to a divide ratio. The method includes providing an auxiliary current through the regulated voltage node. The auxiliary current has a first current level during a first period corresponding to a first value of the divide ratio and the auxiliary current has a second current level during a second period corresponding to a second value of the divide ratio.
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公开(公告)号：US10659060B2
公开(公告)日：2020-05-19
申请号：US16143717
申请日：2018-09-27
Applicant: Silicon Laboratories Inc.
Inventor： Timothy A. Monk , Rajesh Thirugnanam
Abstract: A spur cancellation circuit receives a target spur frequency indicative of a frequency of a spur to be canceled and supplies a spur cancellation signal based on the frequency. A frequency tracking circuit tracks a change in the frequency of the spur to be canceled based on a change in phase of the spur cancellation signal and generates an updated target spur frequency based on the change in the frequency of the spur.
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138.发明授权公开(公告)号：US10659045B2
公开(公告)日：2020-05-19
申请号：US15634716
申请日：2017-06-27
Applicant: Silicon Laboratories Inc.
Inventor： Mohamed M. Elsayed
IPC: G01R31/26 , G11C8/08 , H01L21/70 , H03K17/06 , G11C8/00 , H03K19/00 , H03K19/003 , H03K17/16 , H03K19/0185
Abstract: An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry. The CMOS circuitry includes a p-channel transistor network that includes at least one p-channel transistor having a gate-induced drain leakage (GIDL) current. The IC further includes a native metal oxide semiconductor (MOS) transistor coupled to supply a bias voltage to the at least one p-channel transistor to reduce the GIDL current of the at least one p-channel transistor.
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公开(公告)号：US10658999B1
公开(公告)日：2020-05-19
申请号：US16506409
申请日：2019-07-09
Applicant: Silicon Laboratories Inc.
Inventor： Essam S. Atalla , Ruifeng Sun , Mohamed M. Elkholy
Abstract: Systems and methods are disclosed for on-chip harmonic filtering for radio frequency (RF) communications. A filtering and matching circuit for an integrated circuit includes a first capacitance coupled in parallel with a first inductance, a second inductance coupled to the first inductance, and a variable second capacitance coupled between the first and second inductance. The variable second capacitance is controlled to provide filtering with respect to the RF signal as well as impedance matching with respect to a load coupled to the connection pad. For one embodiment, the variable second capacitance includes a coarse-tune variable capacitor circuit and a fine-tune variable capacitor circuit. The coarse-tuning controls impedance matching, and the fine tuning controls a notch for the filtering. The load can be an antenna for the RF communications. The integrated circuit can include a receive path, a transmit path, or both.
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公开(公告)号：US20200099576A1
公开(公告)日：2020-03-26
申请号：US16137815
申请日：2018-09-21
Applicant: Silicon Laboratories Inc.
Inventor： Christian Salmony Olsen , Jørgen Franck , Peter Shorty , Anders T. Brandt
Abstract: A system and method for improving network resiliency is disclosed. The system includes a network having a plurality of network devices and at least one controller. The controller is configured to create various scenes based on the inputs received from the network devices. The controller is also configured to provide alternate instructions to the network devices in the event that the controller is non-functional. The network devices utilize these alternate instructions when attempts to connect the controller are unsuccessful. In this way, the network is able to operate in a limited way even in the absence of the controller.
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