公开(公告)号：US20080314630A1

公开(公告)日：2008-12-25

申请号：US12213571

申请日：2008-06-20

Applicant: Han Kim ,  Je-Gwang Yoo

Inventor： Han Kim ,  Je-Gwang Yoo

IPC: H01R12/04

CPC classification number: H01P1/2005 ,  H01Q15/006 ,  H01Q15/008 ,  H05K1/0236 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/0969

Abstract: An electromagnetic bandgap structure and a printed circuit board are disclosed. In accordance with an embodiment of the present invention, the electromagnetic bandgap structure includes a mushroom type structure comprising a first metal plate and a via of which one end is connected to the first metal plate; a second metal plate connected to the other end of the via; a first metal layer being connected to the second metal layer through a metal line; a first dielectric layer, layer-built between the first metal layer and the first metal plate; a second dielectric layer, layer-built on the first metal plate and the first dielectric layer; and a second metal layer, layer-built on the second dielectric layer. With the present invention, it is possible to solve the aforementioned mixed signal problem by preventing the EM wave of a certain frequency range from being transferred.

Abstract translation: 公开了电磁带隙结构和印刷电路板。 根据本发明的实施例，电磁带隙结构包括蘑菇型结构，其包括第一金属板和一端连接到第一金属板的通孔; 连接到所述通孔的另一端的第二金属板; 第一金属层通过金属线连接到第二金属层; 在第一金属层和第一金属板之间层叠的第一介电层; 第二电介质层，其在第一金属板和第一介电层上构建; 以及第二金属层，其被构建在第二介电层上。 通过本发明，可以通过防止某一频率范围的EM波被传送来解决上述混合信号问题。

公开(公告)号：US20080264685A1

公开(公告)日：2008-10-30

申请号：US12010437

申请日：2008-01-24

Applicant: Dae-Hyun Park ,  Han Kim ,  Mi-Ja Han ,  Ja-Bu Koo

Inventor： Dae-Hyun Park ,  Han Kim ,  Mi-Ja Han ,  Ja-Bu Koo

IPC: H05K1/11 ,  H01F1/00

CPC classification number: H05K1/0236 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/115 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09781 ,  Y10T29/4913 ,  Y10T29/49165 ,  Y10T428/12465

Abstract: An electromagnetic bandgap structure and a printed circuit board that solve a mixed signal problem are disclosed. In accordance with embodiments of the present invention, the electromagnetic bandgap structure includes a first metal layer; a first dielectric layer, stacked in the first metal layer; a second metal layer, stacked in the first dielectric layer, and having a holed formed at a position of the second dielectric layer; a second dielectric layer, stacked in the second metal layer; a metal plate, stacked in the second dielectric layer; a first via, penetrating the hole formed in the second metal layer and connecting the first metal layer and the metal plate; a third dielectric layer, stacked in the metal plate and the second dielectric layer; a third metal layer, stacked in the third dielectric layer; and a second via, connecting the second metal layer to the third metal layer.

Abstract translation: 公开了一种解决混合信号问题的电磁带隙结构和印刷电路板。 根据本发明的实施例，电磁带隙结构包括第一金属层; 第一介电层，堆叠在第一金属层中; 第二金属层，堆叠在第一介电层中，并且具有形成在第二介电层的位置的孔; 第二介电层，堆叠在第二金属层中; 金属板，堆叠在第二介电层中; 穿过形成在第二金属层中的孔并连接第一金属层和金属板的第一通孔; 第三电介质层，堆叠在所述金属板和所述第二介电层中; 第三金属层，堆叠在第三介电层中; 以及将第二金属层连接到第三金属层的第二通孔。

公开(公告)号：USD560686S1

公开(公告)日：2008-01-29

申请号：US29269150

申请日：2006-11-22

Applicant: Han Kim

Designer： Han Kim

公开(公告)号：USD554149S1

公开(公告)日：2007-10-30

申请号：US29264909

申请日：2006-08-22

Applicant: Han Kim

Designer： Han Kim

公开(公告)号：US07240257B2

公开(公告)日：2007-07-03

申请号：US10994140

申请日：2004-11-19

Applicant: Soon-keun Jeon ,  Yong-cheul Kim ,  Han Kim ,  Bae-sun Jun

Inventor： Soon-keun Jeon ,  Yong-cheul Kim ,  Han Kim ,  Bae-sun Jun

IPC: G11C29/00

CPC classification number: G11C29/14 ,  G11C2029/0405

Abstract: A memory test circuit comprises a memory which outputs stored data through n-bit data output pins, and a built-in self test (BIST) unit. The BIST unit writes test data in the memory, and by comparing the test data output from the memory with expected data, determines a failure cell address in the memory. The BIST unit generates k preliminary failure signals having failure information indicating whether the test data correspond with the expected data, and outputs the k preliminary failure signals for m cycles of a clock signal, by outputting k/m preliminary failure signals each cycle as first through k/m failure signals. In the memory test circuit and test system, the BIST unit testing a memory and generating a failure signal is disposed in a memory apparatus and a failure analysis circuit analyzing a failure signal output by the BIST unit is disposed in the test apparatus.

Abstract translation: 存储器测试电路包括通过n位数据输出引脚输出存储的数据的存储器和内置的自检（BIST）单元。 BIST单元将测试数据写入存储器，并通过将存储器输出的测试数据与预期数据进行比较，确定存储器中的故障单元地址。 BIST单元生成具有指示测试数据是否与期望数据相对应的故障信息的k个初始故障信号，并且通过每个周期作为第一到第一通过输出k / m个初步故障信号来输出用于时钟信号的m个周期的k个初步故障信号 k / m故障信号。 在存储器测试电路和测试系统中，测试存储器并产生故障信号的BIST单元被布置在存储器装置中，并且分析由BIST单元输出的故障信号的故障分析电路设置在测试装置中。

公开(公告)号：US20070082871A1

公开(公告)日：2007-04-12

申请号：US10579199

申请日：2004-11-15

Applicant: Tae Ha ,  Won Kim ,  Sangmin Yun ,  Cheol Kim ,  Han Kim ,  Kwee-Hyun Suh ,  Gwan Lee

Inventor： Tae Ha ,  Won Kim ,  Sangmin Yun ,  Cheol Kim ,  Han Kim ,  Kwee-Hyun Suh ,  Gwan Lee

IPC: A61K31/675 ,  C07F9/6533

CPC classification number: C07D333/56 ,  C07F9/3856 ,  C07F9/386 ,  C07F9/3865 ,  C07F9/3873 ,  C07F9/572 ,  C07F9/58 ,  C07F9/6506

Abstract: The mutual salt of raloxifene and bisphosphonic acid exhibits unexpectedly synergistic effects of two components to enhance bone mineral density (BMD), control blood-calcium density, and lower the serum cholesterol level.

Abstract translation: 雷洛昔芬和双膦酸的相互盐显示两种成分的意外协同效应，以增强骨矿物质密度（BMD），控制血钙密度，降低血清胆固醇水平。

公开(公告)号：US07170384B2

公开(公告)日：2007-01-30

申请号：US11140680

申请日：2005-05-27

Applicant: Han Kim ,  Byoung Youl Min ,  Young Woo Kim ,  Young Jae Lee ,  Chang Myung Ryu

Inventor： Han Kim ,  Byoung Youl Min ,  Young Woo Kim ,  Young Jae Lee ,  Chang Myung Ryu

IPC: H01F5/00

CPC classification number: H01F5/00 ,  H01F17/0006 ,  H01F17/0033 ,  H01F2017/002 ,  H05K1/165 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/097

Abstract: A printed circuit board (PCB) having a three-dimensional spiral inductor, which includes a plurality of insulating layers and conductor layers. The PCB comprises a plurality of coil conductor patterns made of conductive material and shaped into strips, which is provided on the plurality of conductor layers, respectively, such that the plurality of coil conductor patterns are parallel to each other and positioned on the same plane perpendicular to the conductor layers, and in which each of the plurality of coil conductor patterns is longer than an adjacent inner coil conductor pattern.

Abstract translation: 一种具有三维螺旋电感器的印刷电路板（PCB），其包括多个绝缘层和导体层。 PCB包括由导电材料制成并成形为条的多个线圈导体图案，其分别设置在多个导体层上，使得多个线圈导体图案彼此平行并且位于同一平面上垂直 并且其中多个线圈导体图案中的每一个长于相邻的内部线圈导体图案。

公开(公告)号：USD530693S1

公开(公告)日：2006-10-24

申请号：US29237122

申请日：2005-08-26

Applicant: Jung-Hyun Park ,  Han Kim

Designer： Jung-Hyun Park ,  Han Kim

公开(公告)号：US20060210127A1

公开(公告)日：2006-09-21

申请号：US11369325

申请日：2006-03-06

Applicant: Han Kim

Inventor： Han Kim

IPC: G06K9/00

CPC classification number: G06F3/0237 ,  G06K9/00006

Abstract: A mobile communication terminal and method of inserting symbols thereof are disclosed, by which a convenient symbol input system is provided and by which a user is facilitated to input a symbol using a fingerprint pattern of the user. The present invention includes a fingerprint recognizer, a control unit searching a symbol matched to the recognized fingerprint pattern if a fingerprint pattern is recognized by the fingerprint recognizer, and an output unit outputting the searched symbol.

Abstract translation: 公开了一种移动通信终端及其符号的插入方法，通过该移动通信终端和方法，提供方便的符号输入系统，并且通过该移动通信终端便利用户使用指纹图案来输入符号。 本发明包括指纹识别器，如果由指纹识别器识别出指纹图案，则搜索与识别的指纹图案匹配的符号的控制单元，以及输出搜索到的符号的输出单元。

公开(公告)号：US20060207791A1

公开(公告)日：2006-09-21

申请号：US11356524

申请日：2006-02-16

Applicant: Han Kim ,  Chang Ryu ,  Young Lee

Inventor： Han Kim ,  Chang Ryu ,  Young Lee

IPC: H05K1/11 ,  H01K3/10

CPC classification number: H05K1/162 ,  H05K2201/091 ,  H05K2201/09309 ,  H05K2201/09509 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: The present invention relates to a capacitor-embedded PCB and a method of manufacturing the same. The capacitor-embedded PCB includes a dielectric layer, a lower electrode layer formed under the dielectric layer, and an upper electrode layer formed on the dielectric layer and configured to have at least one first blind via hole that is inwardly formed.

Abstract translation: 本发明涉及电容器嵌入式PCB及其制造方法。 电容器嵌入式PCB包括电介质层，在电介质层下形成的下电极层和形成在电介质层上的上电极层，并且被配置为具有至少一个向内形成的第一盲通孔。