公开(公告)号：US20180121344A1

公开(公告)日：2018-05-03

申请号：US15611364

申请日：2017-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONG-YOUNG SEO ,  HONG-MOON WANG

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: A method of operating a storage device managing a multi-namespace includes storing first mapping information including a mapping between a first logical address space and a first physical address space to a mapping table, in response to a request to create a first namespace, the first logical address space being allocated to the first namespace, and storing second mapping information including a mapping between a second logical address space and a second physical address space to the mapping table, in response to a request to create a second namespace, the second logical address space being allocated to the second namespace and being contiguous to the first logical address space.

公开(公告)号：US20180107391A1

公开(公告)日：2018-04-19

申请号：US15296812

申请日：2016-10-18

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Daisuke HASHIMOTO

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/26 ,  G11C16/16 ,  G06F11/10 ,  G11C29/52 ,  G06F12/06

CPC classification number: G11C29/52 ,  G06F3/0617 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/0246 ,  G06F2212/1041 ,  G06F2212/214 ,  G06F2212/222 ,  G06F2212/403 ,  G06F2212/7201 ,  G06F2212/7203 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C29/028 ,  G11C29/42 ,  G11C29/82 ,  G11C2029/4402

Abstract: A storage device includes a nonvolatile memory, a communication interface connectable to a host, and a controller. The controller is configured to carry out writing of data that is received through the communication interface at a physical location of the nonvolatile memory when a write command associated with the data is received through the communication interface, control the communication interface to return a first notification upon determining that the writing of data at the physical location of the nonvolatile memory has completed, and control the communication interface to return a second notification a predetermined period of time after the first notification has been returned.

公开(公告)号：US20180102173A1

公开(公告)日：2018-04-12

申请号：US15835812

申请日：2017-12-08

Applicant: International Business Machines Corporation

Inventor： James S. Fields, JR. ,  Andrew D. Walls

IPC: G11C16/20 ,  G11C16/10 ,  G11C16/26 ,  G06F3/06 ,  G11C16/08 ,  G06F12/0802

CPC classification number: G11C16/20 ,  G06F3/0611 ,  G06F3/0644 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0802 ,  G06F2003/0691 ,  G06F2212/1024 ,  G06F2212/222 ,  G06F2212/7201 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

Abstract: A mechanism is provided for buffer linking in a buffered solid state drive controller. Responsive to the buffered flash memory module receiving from a memory bus of a processor a memory command specifying a write operation, the mechanism initializes a first memory buffer in the buffered flash memory module. The mechanism associates the first memory buffer with an address of the write operation. The mechanism performs a compare operation to compare a previous and a next address with respect, to an address associated with the first memory buffer with a plurality of buffers. The mechanism assigns a link tag to at least one buffer identified in the compare operation and the first memory buffer to form a linked buffer set. The mechanism writes to the first memory buffer based on the memory command. The mechanism builds at least one input/output command to persist contents of the linked buffer set and writes the contents of the linked buffer set to at least one solid state drive according to the at least one input/output command.

公开(公告)号：US20180101302A1

公开(公告)日：2018-04-12

申请号：US15659203

申请日：2017-07-25

Applicant: Silicon Motion, Inc.

Inventor： Wen-Sheng Lin

IPC: G06F3/06 ,  G06F12/10 ,  G06F12/02

CPC classification number: G06F3/0604 ,  G06F3/064 ,  G06F12/0246 ,  G06F12/10 ,  G06F2212/657 ,  G06F2212/7201 ,  G11C16/00

Abstract: A data storage device including a flash memory and a controller is provided. The flash memory has a plurality of TLC blocks, each of which includes a plurality of pages. The controller checks whether any of the TLC blocks was undergoing a write operation and unfinished at the time that the power-off event occurred when the data storage device resumes operation after a power-off event. When a first TLC block was undergoing the write operation and unfinished at the time that the power-off event occurred, the controller further checks whether data stored in a page which was the last one being written in the first TLC block can be successfully read, and continues to write the remaining data into the first TLC block when the data of the page which was the last one being written in the first TLC block can be successfully read.

公开(公告)号：US09940261B2

公开(公告)日：2018-04-10

申请号：US15147465

申请日：2016-05-05

Applicant: HGST Netherlands B.V.

Inventor： Jing Shi Booth ,  Jerry Lo ,  Subhash Balakrishna Pillai

IPC: G06F12/02 ,  G06F12/1009 ,  G06F9/52 ,  G06F3/06

CPC classification number: G06F12/1009 ,  G06F3/0607 ,  G06F3/065 ,  G06F3/0688 ,  G06F9/526 ,  G06F11/1446 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/651 ,  G06F2212/7201 ,  G06F2212/7208

Abstract: An example device includes a memory device and one or more processors. The memory device is configured to store a table that includes two or more mappings, each mapping being associated with a respective logical address and a respective physical address. The processors are configured to identify, within the table, a first zone and a second zone. Each zone includes one or more mappings of the table. The zones do not share any mapping of the table. The processors are further configured to form a first log list indicating one or more mapping updates associated with the mapping(s) included in the first zone, to form a second log list indicating one or more mapping updates associated with the mapping(s) included in the second zone, and to replay a portion of the first log list and a portion of the second log list concurrently to update the table.

公开(公告)号：US09940229B2

公开(公告)日：2018-04-10

申请号：US14496621

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Xipeng Shen ,  Youfeng Wu ,  Cheng Wang ,  Hyunchul Park ,  Hongbo Rong

IPC: G06F12/02

CPC classification number: G06F12/0238 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7207

Abstract: Technologies for persistent memory programming include a computing device having a persistent memory including one or more nonvolatile regions. The computing device may assign a virtual memory address of a target location in persistent memory to a persistent memory pointer using persistent pointer strategy, and may dereference the pointer using the same strategy. Persistent pointer strategies include off-holder, ID-in-value, optimistic rectification, and pessimistic rectification. The computing device may log changes to persistent memory during the execution of a data consistency section, and commit changes to the persistent memory when the last data consistency section ends. Data consistency sections may be grouped by log group identifier. Using type metadata stored in the nonvolatile region, the computing device may identify the type of a root object within the nonvolatile region and then recursively identify the type of all objects referenced by the root object. Other embodiments are described and claimed.

公开(公告)号：US20180096735A1

公开(公告)日：2018-04-05

申请号：US15475902

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： LAKSHMINARAYANA PAPPU

IPC: G11C29/14 ,  H01L25/18 ,  H01L25/065 ,  G11C11/4096 ,  G11C5/06 ,  G06F3/06

CPC classification number: G11C29/14 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06F2212/7201 ,  G11C5/025 ,  G11C5/063 ,  G11C11/4096 ,  G11C29/022 ,  G11C29/16 ,  G11C29/70 ,  G11C2029/0401 ,  G11C2029/4402 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06544

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing testing of a far memory subsystem within Two-Level Memory (2LM) stacked die subsystems. For instance, there is in accordance with one embodiment a stacked semiconductor package which includes: a functional silicon die; a test controller having signature accumulation logic embedded therein; a fabric to route transactions between the test controller and a far memory controller of the functional silicon die; in which the far memory controller includes a physical memory interface having no physical memory attached; a Two Level Memory (2LM) controller having logic to modify received transactions to indicate a cache miss forcing all received transactions to be routed to the far memory controller via the fabric; and an auto response mechanism to observe the transactions on the fabric and route responses and completions issued in reply to the transactions back to an agent having initiated the transactions. Other related embodiments are disclosed.

公开(公告)号：US20180095678A1

公开(公告)日：2018-04-05

申请号：US15388892

申请日：2016-12-22

Applicant: Cypress Semiconductor Corporation

Inventor： Mark Alan McClain ,  Willy Obereiner ,  Rainer Hoehler

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/064 ,  G06F3/0644 ,  G06F3/0649 ,  G06F3/0653 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/1041 ,  G06F2212/7201 ,  G06F2212/7211

Abstract: Disclosed herein are systems, methods, and devices for user configurable wear leveling of non-volatile memory devices. Devices include a non-volatile memory including a plurality of physical memory portions, where each of the plurality of physical memory portions is configured to be mapped to a logical memory portion of a plurality of logical memory portions. Devices may also include wear leveling control circuitry configured to receive a plurality of wear leveling parameters, and further configured to determine a plurality of wear leveling characteristics based on the plurality of wear leveling parameters received, where the plurality of wear leveling characteristics identify an amount of wear leveling allowed for each of the plurality of logical memory portions.

公开(公告)号：US09933842B2

公开(公告)日：2018-04-03

申请号：US15487426

申请日：2017-04-13

Applicant: Emerson Climate Technologies, Inc.

Inventor： Charles E. Green ,  Joseph G. Marcinkiewicz

IPC: H02M1/42 ,  G06F1/32 ,  H02P29/02 ,  G06F9/445 ,  G06F13/42 ,  G06F13/40 ,  G06F9/22 ,  G06F12/02

CPC classification number: G06F1/3287 ,  G06F8/61 ,  G06F8/654 ,  G06F9/223 ,  G06F12/0246 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/7201 ,  H02M1/32 ,  H02M1/36 ,  H02M1/42 ,  H02M1/4225 ,  H02M2001/0012 ,  H02M2001/327 ,  H02M2001/4291 ,  H02P29/02

Abstract: A circuit for driving a motor of a compressor includes a microcontroller, which includes an op-amp, a comparator, a first serial interface, and a first dedicated pin. The op-amp amplifies a value indicating current in a power factor correction converter, which includes a power switch. The comparator asserts a comparison signal in response to the amplified value exceeding a reference value. The comparison signal is output on the first dedicated pin. A programmable logic device (PLD) includes a second serial interface in communication with the first serial interface and a second dedicated pin. The comparison signal is received on the second dedicated pin and the PLD receives control messages from the microcontroller via the second serial interface. The PLD sets a value in an off-time register based on a control message from the microcontroller. The PLD controls the power switch according to the comparison signal and the off-time register.

公开(公告)号：US20180089134A1

公开(公告)日：2018-03-29

申请号：US15824456

申请日：2017-11-28

Applicant: Google LLC

Inventor： Katie Leah Roberts-Hoffman ,  Alberto Martin Perez

IPC: G06F13/40 ,  G06F1/16 ,  G06F13/38 ,  G11C7/10 ,  G06F13/42 ,  G06F21/71 ,  G06F12/02

CPC classification number: G06F13/4081 ,  G06F1/1605 ,  G06F1/1613 ,  G06F1/1616 ,  G06F1/1632 ,  G06F12/0246 ,  G06F13/382 ,  G06F13/4282 ,  G06F21/71 ,  G06F2212/7201 ,  G11C7/1072

Abstract: In one general aspect, a main printed circuit board (PCB) card can include a System on a Chip (SoC) configured to run an operating system stored on the main PCB card, at least one dynamic random access memory (DRAM) device and at least one non-volatile memory device each configured for use by the SoC, and at least one connector. The main PCB card can be configured to be interchangeably interfaced with multiple types of shell computing devices by way of a slot included in a shell computing device. The slot can be configured to accommodate the main PCB card. Each type of shell computing device can be of a different form factor. Each form factor can be representative of a different type of computing device. The at least one connector can be configured to be plugged into a mating connector included in a shell computing device.