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    Data organization for logical to physical table compression
    1.
    发明授权
    Data organization for logical to physical table compression 有权

    公开(公告)号：US12124365B2

    公开(公告)日：2024-10-22

    申请号：US17420210

    申请日：2021-05-05

    Applicant: Micron Technology, Inc.

    Inventor： Yanhua Bi

    IPC: G06F12/02 ,  G06F13/16

    CPC classification number: G06F12/0246 ,  G06F13/1668 ,  G06F2212/401 ,  G06F2212/7201

    Abstract: Methods, systems, and devices for data organization for logical to physical table compression are described. The memory system may identify a region that includes one or more logical addresses associated with discontinuous corresponding physical addresses. The memory system may include a plurality of regions of logical addresses and a plurality of memory cells arranged according to a plurality of physical addresses. The memory system may determine a period of inactivity of access operations on the plurality of memory cells and rearrange, during the period of inactivity, information stored within the discontinuous corresponding physical addresses to be within continuous physical addresses of the plurality of physical addresses.

    Using a flag to indicate whether a mapping entry points to sequentially stored data
    5.
    发明授权
    Using a flag to indicate whether a mapping entry points to sequentially stored data 有权

    公开(公告)号：US12099449B2

    公开(公告)日：2024-09-24

    申请号：US18048364

    申请日：2022-10-20

    Applicant: Micron Technology, Inc.

    Inventor： Giuseppe Cariello ,  Jonathan S. Parry

    IPC: G06F12/1009

    CPC classification number: G06F12/1009 ,  G06F2212/651 ,  G06F2212/7201

    Abstract: Methods, systems, and devices for compressed logical-to-physical mapping for sequentially stored data are described. A memory device may use a hierarchical set of logical-to-physical mapping tables for mapping logical block address generated by a host device to physical addresses of the memory device. The memory device may determine whether all of the entries of a terminal logical-to-physical mapping table are consecutive physical addresses. In response to determining that all of the entries contain consecutive physical addresses, the memory device may store a starting physical address of the consecutive physical addresses as an entry in a higher-level table along with a flag indicating that the entry points directly to data in the memory device rather than pointing to a terminal logical-to-physical mapping table. The memory device may, for subsequent reads of data stored in one or more of the consecutive physical addresses, bypass the terminal table to read the data.

    MEMORY SYSTEM
    8.
    发明公开
    MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240281370A1

    公开(公告)日：2024-08-22

    申请号：US18581505

    申请日：2024-02-20

    Applicant: Kioxia Corporation

    Inventor： Hirotsugu KAJIHARA ,  Yu NAKANISHI ,  Kohei OIKAWA ,  Kazuhiro HIWADA

    IPC: G06F12/02

    CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7205

    Abstract: According to one embodiment, a memory system includes: a nonvolatile memory including blocks each of which includes physical memory areas; and a memory controller dividing a logical address space into a plurality of banks and associating a block with each of the plurality of banks. The memory controller is configured to: selectively scan a portion related to a first bank among the plurality of banks in a table in which a physical address corresponding to a physical memory area in which valid data is stored is mapped on the logical address space; detect a first physical address corresponding to a first physical memory area in a first block associated with the first bank as a result of the scan; read first valid data stored in the first block based on the first physical address; and write the first valid data in a second block associated with the first bank.

    ATOMIC WRITE OPERATIONS
    9.
    发明公开
    ATOMIC WRITE OPERATIONS 审中-公开

    公开(公告)号：US20240281367A1

    公开(公告)日：2024-08-22

    申请号：US18591942

    申请日：2024-02-29

    Applicant: Micron Technology, Inc.

    Inventor： Giuseppe Cariello

    IPC: G06F12/02

    CPC classification number: G06F12/0238 ,  G06F2212/7201

    Abstract: Methods, systems, and devices for atomic write operations are described. A host system may receive a sequence of data that includes a first set of data and a second set of data. The host system may determine, based on the sequence of data, a first set of contiguous logical addresses for the first set of data and a second set of contiguous logical address for the second set of data. The host system may then transmit to a memory system a write command that indicates the first set of contiguous logical addresses and the second set of contiguous logical addresses. The first set of contiguous logical addresses may be discontiguous with the second set of contiguous logical addresses.

    Address translation based on page identifier and queue identifier
    10.
    发明授权
    Address translation based on page identifier and queue identifier 有权

    公开(公告)号：US12066949B2

    公开(公告)日：2024-08-20

    申请号：US17541786

    申请日：2021-12-03

    Applicant: Micron Technology, Inc.

    Inventor： Chung Kuang Chin ,  Di Hsien Ngu ,  Horia C. Simionescu

    IPC: G06F12/1009

    CPC classification number: G06F12/1009 ,  G06F2212/651 ,  G06F2212/7201

    Abstract: Translated addresses of a memory device can be stored in a first LUT maintained by control circuitry. Untranslated addresses can be stored in a second LUT maintained by the control circuitry. In response to a translation request for a particular translated address of the memory device corresponding to a target untranslated address, an index of the second LUT associated with the target untranslated address can be determined, the index of the second LUT can be mapped to an index of the first LUT, and the particular translated address corresponding to the target untranslated address can be retrieved from the first LUT.

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